[people/ms/u-boot.git] / include / configs / redwood.h

/*
 * Configuration for AMCC 460SX Ref (redwood)
 *
 * (C) Copyright 2008
 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_440			1	/* ... PPC460 family	*/
#define CONFIG_460SX			1	/* ... PPC460 family	*/

#define	CONFIG_SYS_TEXT_BASE	0xfffb0000

/*-----------------------------------------------------------------------
 * Include common defines/options for all AMCC boards
 *----------------------------------------------------------------------*/
#define CONFIG_HOSTNAME		redwood

#include "amcc-common.h"

#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0xfff00000	/* start of FLASH	*/
#define CONFIG_SYS_ISRAM_BASE		0x90000000	/* internal SRAM	*/

#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/

#define CONFIG_SYS_PCIE_MEMBASE	0x90000000	/* mapped PCIe memory	*/
#define CONFIG_SYS_PCIE0_MEMBASE	0x90000000	/* mapped PCIe memory	*/
#define CONFIG_SYS_PCIE1_MEMBASE	0xa0000000	/* mapped PCIe memory	*/
#define CONFIG_SYS_PCIE_MEMSIZE	0x01000000

#define CONFIG_SYS_PCIE0_XCFGBASE	0xb0000000
#define CONFIG_SYS_PCIE1_XCFGBASE	0xb2000000
#define CONFIG_SYS_PCIE2_XCFGBASE	0xb4000000
#define CONFIG_SYS_PCIE0_CFGBASE	0xb6000000
#define CONFIG_SYS_PCIE1_CFGBASE	0xb8000000
#define CONFIG_SYS_PCIE2_CFGBASE	0xba000000

/* PCIe mapped UTL registers */
#define CONFIG_SYS_PCIE0_REGBASE   0xd0000000
#define CONFIG_SYS_PCIE1_REGBASE   0xd0010000
#define CONFIG_SYS_PCIE2_REGBASE   0xd0020000

/* System RAM mapped to PCI space */
#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)

#define CONFIG_SYS_FPGA_BASE		0xe2000000	/* epld			*/
#define CONFIG_SYS_OPER_FLASH		0xe7000000	/* SRAM - OPER Flash	*/

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1	/* Use UART0			*/

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CONFIG_SPD_EEPROM	1	/* Use SPD EEPROM for setup	*/
#define CONFIG_DDR_ECC		1	/* with ECC support		*/

#define CONFIG_SYS_SPD_MAX_DIMMS	2

/* SPD i2c spd addresses */
#define SPD_EEPROM_ADDRESS     {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
#define IIC0_DIMM0_ADDR		       0x53
#define IIC0_DIMM1_ADDR		       0x52

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000

#define IIC0_BOOTPROM_ADDR	0x50
#define IIC0_ALT_BOOTPROM_ADDR	0x54

/* Don't probe these addrs */
#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }

#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#undef	CONFIG_ENV_IS_IN_NVRAM		/* ... not in NVRAM		*/
#define	CONFIG_ENV_IS_IN_FLASH	1	/* Environment uses flash	*/
#undef	CONFIG_ENV_IS_IN_EEPROM		/* ... not in EEPROM		*/

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"fdt_addr=fc1e0000\0"						\
	"ramdisk_addr=fc200000\0"					\
	""

/*----------------------------------------------------------------------------+
| Commands in addition to amcc-common.h
+----------------------------------------------------------------------------*/
#define CONFIG_CMD_SDRAM

#define CONFIG_BOOTCOMMAND	"run flash_self"


#define	CONFIG_IBM_EMAC4_V4	1
#define CONFIG_PHY_RESET	1	/* reset phy upon startup	*/
#define CONFIG_PHY_RESET_DELAY	1000
#define CONFIG_M88E1141_PHY	1	/* Enable phy */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/
#define CONFIG_PHY1_ADDR	1	/* PHY address, See schematics	*/

#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI			/* The flash is CFI compatible	*/
#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1	/* Use AMD (Spansion) reset cmd */

#define CONFIG_SYS_MAX_FLASH_BANKS	3	/* number of banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* sectors per device		*/

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms) */

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		0xfffa0000
#define CONFIG_ENV_SIZE		0x10000	/* Size of Environment vars	*/
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*---------------------------------------------------------------------------*/

#endif	/* __CONFIG_H */
Commit	Line	Data
96e5fc0e FK	1	/*
	2	* Configuration for AMCC 460SX Ref (redwood)
	3	*
	4	* (C) Copyright 2008
	5	* Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
96e5fc0e FK	8	*/
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*-----------------------------------------------------------------------
	13	* High Level Configuration Options
	14	----------------------------------------------------------------------/
96e5fc0e FK	15	#define CONFIG_440 1 /* ... PPC460 family */
96e5fc0e FK	16	#define CONFIG_460SX 1 /* ... PPC460 family */
96e5fc0e	17
2ae18241 WD	18	#define CONFIG_SYS_TEXT_BASE 0xfffb0000
2ae18241 WD	19
96e5fc0e FK	20	/*-----------------------------------------------------------------------
	21	* Include common defines/options for all AMCC boards
	22	----------------------------------------------------------------------/
	23	#define CONFIG_HOSTNAME redwood
	24
	25	#include "amcc-common.h"
	26
	27	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	28
	29	/*-----------------------------------------------------------------------
	30	* Base addresses -- Note these are effective addresses where the
	31	* actual resources get mapped (not physical addresses)
	32	----------------------------------------------------------------------/
6d0f6bcf	33	#define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */
6d0f6bcf	34	#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
96e5fc0e	35
6d0f6bcf	36	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
96e5fc0e	37
6d0f6bcf JCPV	38	#define CONFIG_SYS_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
	39	#define CONFIG_SYS_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */
	40	#define CONFIG_SYS_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */
	41	#define CONFIG_SYS_PCIE_MEMSIZE 0x01000000
8f2b457e	42
6d0f6bcf JCPV	43	#define CONFIG_SYS_PCIE0_XCFGBASE 0xb0000000
	44	#define CONFIG_SYS_PCIE1_XCFGBASE 0xb2000000
	45	#define CONFIG_SYS_PCIE2_XCFGBASE 0xb4000000
	46	#define CONFIG_SYS_PCIE0_CFGBASE 0xb6000000
	47	#define CONFIG_SYS_PCIE1_CFGBASE 0xb8000000
	48	#define CONFIG_SYS_PCIE2_CFGBASE 0xba000000
96e5fc0e FK	49
96e5fc0e FK	50	/* PCIe mapped UTL registers */
6d0f6bcf JCPV	51	#define CONFIG_SYS_PCIE0_REGBASE 0xd0000000
	52	#define CONFIG_SYS_PCIE1_REGBASE 0xd0010000
	53	#define CONFIG_SYS_PCIE2_REGBASE 0xd0020000
96e5fc0e FK	54
96e5fc0e FK	55	/* System RAM mapped to PCI space */
6d0f6bcf JCPV	56	#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
6d0f6bcf JCPV	57	#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
96e5fc0e FK	58	#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
96e5fc0e FK	59
6d0f6bcf JCPV	60	#define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */
6d0f6bcf JCPV	61	#define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
96e5fc0e	62
550650dd SR	63	/*
	64	* Serial Port
	65	*/
	66	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	67
96e5fc0e FK	68	/*-----------------------------------------------------------------------
	69	* Initial RAM & stack pointer (placed in internal SRAM)
	70	----------------------------------------------------------------------/
6d0f6bcf JCPV	71	#define CONFIG_SYS_TEMP_STACK_OCM 1
	72	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	73	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	74	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
96e5fc0e	75
25ddd1fb	76	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	77	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
96e5fc0e FK	78
	79	/*-----------------------------------------------------------------------
	80	* DDR SDRAM
	81	----------------------------------------------------------------------/
	82	#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
	83	#define CONFIG_DDR_ECC 1 /* with ECC support */
	84
6d0f6bcf	85	#define CONFIG_SYS_SPD_MAX_DIMMS 2
96e5fc0e FK	86
	87	/* SPD i2c spd addresses */
	88	#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR}
8f2b457e HS	89	#define IIC0_DIMM0_ADDR 0x53
8f2b457e HS	90	#define IIC0_DIMM1_ADDR 0x52
96e5fc0e FK	91
	92	/*-----------------------------------------------------------------------
	93	* I2C
	94	----------------------------------------------------------------------/
880540de	95	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
96e5fc0e FK	96
	97	#define IIC0_BOOTPROM_ADDR 0x50
	98	#define IIC0_ALT_BOOTPROM_ADDR 0x54
	99
	100	/* Don't probe these addrs */
880540de	101	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x50}, {0, 0x52}, {0, 0x53}, {0, 0x54} }
96e5fc0e	102
6d0f6bcf	103	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
96e5fc0e FK	104
	105	/*-----------------------------------------------------------------------
	106	* Environment
	107	----------------------------------------------------------------------/
9314cee6	108	#undef CONFIG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
5a1aceb0	109	#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
bb1f8b4f	110	#undef CONFIG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
96e5fc0e FK	111
	112	#define CONFIG_PREBOOT "echo;" \
	113	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	114	"echo"
	115
	116	#undef CONFIG_BOOTARGS
	117
	118	#define CONFIG_EXTRA_ENV_SETTINGS \
8f2b457e HS	119	CONFIG_AMCC_DEF_ENV \
	120	CONFIG_AMCC_DEF_ENV_POWERPC \
	121	CONFIG_AMCC_DEF_ENV_NOR_UPD \
8f2b457e HS	122	"kernel_addr=fc000000\0" \
	123	"fdt_addr=fc1e0000\0" \
	124	"ramdisk_addr=fc200000\0" \
96e5fc0e FK	125	""
	126
	127	/*----------------------------------------------------------------------------+
	128	\| Commands in addition to amcc-common.h
	129	+----------------------------------------------------------------------------*/
	130	#define CONFIG_CMD_SDRAM
	131
	132	#define CONFIG_BOOTCOMMAND "run flash_self"
	133
96e5fc0e FK	134
96e5fc0e FK	135	#define CONFIG_IBM_EMAC4_V4 1
8f2b457e	136	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
96e5fc0e FK	137	#define CONFIG_PHY_RESET_DELAY 1000
	138	#define CONFIG_M88E1141_PHY 1 /* Enable phy */
	139	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	140
	141	#define CONFIG_HAS_ETH0
	142	#define CONFIG_HAS_ETH1
	143	#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
	144	#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */
	145
	146	#undef CONFIG_WATCHDOG /* watchdog disabled */
	147
	148	/*-----------------------------------------------------------------------
	149	* FLASH related
	150	----------------------------------------------------------------------/
6d0f6bcf	151	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
8f2b457e	152	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf	153	#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
96e5fc0e	154
6d0f6bcf JCPV	155	#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
6d0f6bcf JCPV	156	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
96e5fc0e	157
6d0f6bcf JCPV	158	#undef CONFIG_SYS_FLASH_CHECKSUM
	159	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	160	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
96e5fc0e	161
5a1aceb0	162	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586 JCPV	163	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
	164	#define CONFIG_ENV_ADDR 0xfffa0000
	165	#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment vars */
5a1aceb0	166	#endif /* CONFIG_ENV_IS_IN_FLASH */
96e5fc0e FK	167
	168	/---------------------------------------------------------------------------/
	169
	170	#endif /* __CONFIG_H */