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85a3cfb8 KY |
1 | /* |
2 | * (C) Copyright 2016 Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __CONFIG_RK3328_COMMON_H | |
8 | #define __CONFIG_RK3328_COMMON_H | |
9 | ||
10 | #include "rockchip-common.h" | |
11 | ||
85a3cfb8 KY |
12 | #define CONFIG_SYS_MALLOC_LEN (32 << 20) |
13 | #define CONFIG_SYS_CBSIZE 1024 | |
14 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
15 | ||
16 | #define CONFIG_SYS_NS16550_MEM32 | |
17 | ||
85a3cfb8 KY |
18 | #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 |
19 | #define CONFIG_SYS_LOAD_ADDR 0x00800800 | |
20 | ||
21 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ | |
22 | ||
23 | /* MMC/SD IP block */ | |
24 | #define CONFIG_BOUNCE_BUFFER | |
25 | ||
85a3cfb8 KY |
26 | /* RAW SD card / eMMC locations. */ |
27 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) | |
28 | ||
29 | /* FAT sd card locations. */ | |
30 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 | |
31 | #define CONFIG_SYS_SDRAM_BASE 0 | |
32 | #define CONFIG_NR_DRAM_BANKS 1 | |
6d1970fa | 33 | #define SDRAM_MAX_SIZE 0xff000000 |
85a3cfb8 KY |
34 | |
35 | #define CONFIG_SPI_FLASH | |
36 | #define CONFIG_SPI | |
37 | #define CONFIG_SF_DEFAULT_SPEED 20000000 | |
38 | ||
39 | #ifndef CONFIG_SPL_BUILD | |
40 | ||
41 | #define ENV_MEM_LAYOUT_SETTINGS \ | |
42 | "scriptaddr=0x00500000\0" \ | |
43 | "pxefile_addr_r=0x00600000\0" \ | |
44 | "fdt_addr_r=0x01f00000\0" \ | |
45 | "kernel_addr_r=0x02000000\0" \ | |
46 | "ramdisk_addr_r=0x04000000\0" | |
47 | ||
48 | #include <config_distro_bootcmd.h> | |
49 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
50 | ENV_MEM_LAYOUT_SETTINGS \ | |
51 | "partitions=" PARTS_DEFAULT \ | |
52 | BOOTENV | |
53 | ||
54 | #endif | |
55 | ||
d16f514d MD |
56 | /* rockchip ohci host driver */ |
57 | #define CONFIG_USB_OHCI_NEW | |
58 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 | |
4f3a579e | 59 | |
85a3cfb8 | 60 | #endif |