[people/ms/u-boot.git] / include / configs / rsk7203.h

/*
 * Configuation settings for the Renesas Technology RSK 7203
 *
 * Copyright (C) 2008 Nobuhiro Iwamatsu
 * Copyright (C) 2008 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __RSK7203_H
#define __RSK7203_H

#define CONFIG_CPU_SH7203	1

#define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */

#define CONFIG_DISPLAY_BOARDINFO
#undef	CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define RSK7203_SDRAM_BASE	0x0C000000
#define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
#define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)

/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_CONS_SCIF0	1

#define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))

#define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#undef	CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT	64
#define CONFIG_SYS_MAX_FLASH_BANKS	1

#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT	12000
#define CONFIG_SYS_FLASH_WRITE_TOUT	500

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)

#endif	/* __RSK7203_H */
Commit	Line	Data
c655fad0 NI	1	/*
	2	* Configuation settings for the Renesas Technology RSK 7203
	3	*
	4	* Copyright (C) 2008 Nobuhiro Iwamatsu
	5	* Copyright (C) 2008 Renesas Solutions Corp.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
c655fad0 NI	8	*/
	9
	10	#ifndef __RSK7203_H
	11	#define __RSK7203_H
	12
c655fad0	13	#define CONFIG_CPU_SH7203 1
c655fad0	14
c655fad0 NI	15	#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
c655fad0 NI	16
18a40e84	17	#define CONFIG_DISPLAY_BOARDINFO
c655fad0 NI	18	#undef CONFIG_SHOW_BOOT_PROGRESS
	19
	20	/* MEMORY */
	21	#define RSK7203_SDRAM_BASE 0x0C000000
	22	#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
	23	#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
	24
c655fad0	25	/* List of legal baudrate settings for this board */
6d0f6bcf	26	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
c655fad0 NI	27
c655fad0 NI	28	/* SCIF */
c655fad0 NI	29	#define CONFIG_CONS_SCIF0 1
c655fad0 NI	30
6d0f6bcf JCPV	31	#define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE
6d0f6bcf JCPV	32	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
c655fad0	33
6d0f6bcf JCPV	34	#define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE
6d0f6bcf JCPV	35	#define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024)
c655fad0	36
6d0f6bcf JCPV	37	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
	38	#define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1
	39	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
	40	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	41	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
c655fad0 NI	42
c655fad0 NI	43	/* FLASH */
6f3d8bb5	44	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	45	#define CONFIG_SYS_FLASH_CFI
	46	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	47	#undef CONFIG_SYS_FLASH_QUIET_TEST
	48	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	49	#define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1
	50	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
	51	#define CONFIG_SYS_MAX_FLASH_SECT 64
	52	#define CONFIG_SYS_MAX_FLASH_BANKS 1
c655fad0	53
0e8d1586 JCPV	54	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
0e8d1586 JCPV	55	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
6d0f6bcf JCPV	56	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	57	#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
	58	#define CONFIG_SYS_FLASH_WRITE_TOUT 500
c655fad0 NI	59
	60	/* Board Clock */
	61	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	62	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	63	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
c655fad0	64	#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
8f0960e8	65	#define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
c655fad0 NI	66
c655fad0 NI	67	#endif /* __RSK7203_H */