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Commit | Line | Data |
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c655fad0 NI |
1 | /* |
2 | * Configuation settings for the Renesas Technology RSK 7203 | |
3 | * | |
4 | * Copyright (C) 2008 Nobuhiro Iwamatsu | |
5 | * Copyright (C) 2008 Renesas Solutions Corp. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
c655fad0 NI |
8 | */ |
9 | ||
10 | #ifndef __RSK7203_H | |
11 | #define __RSK7203_H | |
12 | ||
13 | #undef DEBUG | |
14 | #define CONFIG_SH 1 | |
15 | #define CONFIG_SH2 1 | |
16 | #define CONFIG_SH2A 1 | |
17 | #define CONFIG_CPU_SH7203 1 | |
18 | #define CONFIG_RSK7203 1 | |
19 | ||
20 | #define CONFIG_CMD_FLASH | |
21 | #define CONFIG_CMD_NET | |
22 | #define CONFIG_CMD_NFS | |
23 | #define CONFIG_CMD_PING | |
bdab39d3 | 24 | #define CONFIG_CMD_SAVEENV |
c655fad0 NI |
25 | #define CONFIG_CMD_SDRAM |
26 | #define CONFIG_CMD_MEMORY | |
27 | #define CONFIG_CMD_CACHE | |
28 | ||
29 | #define CONFIG_BAUDRATE 115200 | |
30 | #define CONFIG_BOOTARGS "console=ttySC0,115200" | |
31 | #define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */ | |
32 | ||
33 | #define CONFIG_VERSION_VARIABLE | |
34 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
35 | ||
36 | /* MEMORY */ | |
37 | #define RSK7203_SDRAM_BASE 0x0C000000 | |
38 | #define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */ | |
39 | #define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024) | |
40 | ||
4f9a5b06 | 41 | #define CONFIG_SYS_TEXT_BASE 0x0C7C0000 |
6d0f6bcf JCPV |
42 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
43 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
44 | #define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */ | |
45 | #define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ | |
46 | #define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */ | |
c655fad0 | 47 | /* Buffer size for Boot Arguments passed to kernel */ |
6d0f6bcf | 48 | #define CONFIG_SYS_BARGSIZE 512 |
c655fad0 | 49 | /* List of legal baudrate settings for this board */ |
6d0f6bcf | 50 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } |
c655fad0 NI |
51 | |
52 | /* SCIF */ | |
6f3d8bb5 | 53 | #define CONFIG_SCIF_CONSOLE 1 |
c655fad0 NI |
54 | #define CONFIG_CONS_SCIF0 1 |
55 | ||
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_MEMTEST_START RSK7203_SDRAM_BASE |
57 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024)) | |
c655fad0 | 58 | |
6d0f6bcf JCPV |
59 | #define CONFIG_SYS_SDRAM_BASE RSK7203_SDRAM_BASE |
60 | #define CONFIG_SYS_SDRAM_SIZE (32 * 1024 * 1024) | |
c655fad0 | 61 | |
6d0f6bcf JCPV |
62 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024) |
63 | #define CONFIG_SYS_MONITOR_BASE RSK7203_FLASH_BASE_1 | |
64 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) | |
65 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) | |
6d0f6bcf | 66 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
c655fad0 NI |
67 | |
68 | /* FLASH */ | |
6f3d8bb5 | 69 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
70 | #define CONFIG_SYS_FLASH_CFI |
71 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
72 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
73 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ | |
74 | #define CONFIG_SYS_FLASH_BASE RSK7203_FLASH_BASE_1 | |
75 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } | |
76 | #define CONFIG_SYS_MAX_FLASH_SECT 64 | |
77 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
c655fad0 | 78 | |
5a1aceb0 | 79 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 JCPV |
80 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) |
81 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE | |
6d0f6bcf JCPV |
82 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
83 | #define CONFIG_SYS_FLASH_ERASE_TOUT 12000 | |
84 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
c655fad0 NI |
85 | |
86 | /* Board Clock */ | |
87 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
88 | #define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */ | |
6d0f6bcf | 89 | #define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) |
c655fad0 | 90 | |
05c7e907 | 91 | /* Network interface */ |
736fead8 BW |
92 | #define CONFIG_SMC911X |
93 | #define CONFIG_SMC911X_16_BIT | |
94 | #define CONFIG_SMC911X_BASE (0x24000000) | |
05c7e907 | 95 | |
c655fad0 | 96 | #endif /* __RSK7203_H */ |