[people/ms/u-boot.git] / include / configs / sama5d3_xplained.h

/*
 * Configuration settings for the SAMA5D3 Xplained board.
 *
 * Copyright (C) 2014 Atmel Corporation
 *		      Bo Shen <voice.shen@atmel.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "at91-sama5_common.h"

/*
 * This needs to be defined for the OHCI code to work but it is defined as
 * ATMEL_ID_UHPHS in the CPU specific header files.
 */
#define ATMEL_ID_UHP			32

/*
 * Specify the clock enable bit in the PMC_SCER register.
 */
#define ATMEL_PMC_UHP			(1 <<  6)

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE           0x20000000
#define CONFIG_SYS_SDRAM_SIZE		0x10000000

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_INIT_SP_ADDR		0x318000
#else
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
#endif

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x60000000
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
#define CONFIG_SYS_NAND_ONFI_DETECTION

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP		4
#define CONFIG_PMECC_SECTOR_SIZE	512

/* USB */

#ifdef CONFIG_CMD_USB
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00600000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"SAMA5D3 Xplained"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#endif

#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */

/* SPL */
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		0x18000
#define CONFIG_SPL_BSS_START_ADDR	0x20000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)

#ifdef CONFIG_SD_BOOT
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#endif
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER

#endif
Commit	Line	Data
7ca6f363 BS	1	/*
	2	* Configuration settings for the SAMA5D3 Xplained board.
	3	*
	4	* Copyright (C) 2014 Atmel Corporation
	5	* Bo Shen <voice.shen@atmel.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
b2d387bc	13	#include "at91-sama5_common.h"
7ca6f363	14
7ca6f363 BS	15	/*
	16	* This needs to be defined for the OHCI code to work but it is defined as
	17	* ATMEL_ID_UHPHS in the CPU specific header files.
	18	*/
e61ed48f	19	#define ATMEL_ID_UHP 32
7ca6f363 BS	20
	21	/*
	22	* Specify the clock enable bit in the PMC_SCER register.
	23	*/
e61ed48f	24	#define ATMEL_PMC_UHP (1 << 6)
7ca6f363	25
7ca6f363 BS	26	/* SDRAM */
7ca6f363 BS	27	#define CONFIG_NR_DRAM_BANKS 1
e61ed48f	28	#define CONFIG_SYS_SDRAM_BASE 0x20000000
7ca6f363 BS	29	#define CONFIG_SYS_SDRAM_SIZE 0x10000000
7ca6f363 BS	30
cd23aac4	31	#ifdef CONFIG_SPL_BUILD
1878804a	32	#define CONFIG_SYS_INIT_SP_ADDR 0x318000
cd23aac4	33	#else
7ca6f363	34	#define CONFIG_SYS_INIT_SP_ADDR \
1878804a	35	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
cd23aac4	36	#endif
7ca6f363 BS	37
7ca6f363 BS	38	/* NAND flash */
7ca6f363 BS	39	#ifdef CONFIG_CMD_NAND
	40	#define CONFIG_NAND_ATMEL
	41	#define CONFIG_SYS_MAX_NAND_DEVICE 1
e61ed48f	42	#define CONFIG_SYS_NAND_BASE 0x60000000
7ca6f363 BS	43	/* our ALE is AD21 */
	44	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	45	/* our CLE is AD22 */
	46	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	47	#define CONFIG_SYS_NAND_ONFI_DETECTION
8f1a80e9 TR	48
	49	#define CONFIG_MTD_DEVICE
	50	#define CONFIG_MTD_PARTITIONS
	51	#endif
7ca6f363 BS	52	/* PMECC & PMERRLOC */
	53	#define CONFIG_ATMEL_NAND_HWECC
	54	#define CONFIG_ATMEL_NAND_HW_PMECC
	55	#define CONFIG_PMECC_CAP 4
	56	#define CONFIG_PMECC_SECTOR_SIZE 512
7ca6f363	57
7ca6f363	58	/* USB */
7ca6f363 BS	59
	60	#ifdef CONFIG_CMD_USB
	61	#define CONFIG_USB_ATMEL
	62	#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
	63	#define CONFIG_USB_OHCI_NEW
	64	#define CONFIG_SYS_USB_OHCI_CPU_INIT
e61ed48f	65	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000
7ca6f363 BS	66	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained"
7ca6f363 BS	67	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
7ca6f363 BS	68	#endif
7ca6f363 BS	69
7ca6f363 BS	70	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
7ca6f363 BS	71
cd23aac4	72	/* SPL */
cd23aac4	73	#define CONFIG_SPL_TEXT_BASE 0x300000
1878804a	74	#define CONFIG_SPL_MAX_SIZE 0x18000
cd23aac4 BS	75	#define CONFIG_SPL_BSS_START_ADDR 0x20000000
	76	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	77	#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
	78	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	79
cd23aac4 BS	80	#define CONFIG_SYS_MONITOR_LEN (512 << 10)
cd23aac4 BS	81
5541543f	82	#ifdef CONFIG_SD_BOOT
e2ccdf89	83	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	84	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
cd23aac4	85
5541543f	86	#elif CONFIG_NAND_BOOT
cd23aac4 BS	87	#define CONFIG_SPL_NAND_DRIVERS
cd23aac4 BS	88	#define CONFIG_SPL_NAND_BASE
5541543f	89	#endif
cd23aac4 BS	90	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	91	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	92	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	93	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	94	#define CONFIG_SYS_NAND_OOBSIZE 64
	95	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	96	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
05a4d544	97	#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
cd23aac4 BS	98
cd23aac4 BS	99	#endif