]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/sandbox.h
block: Migrate SystemACE chip to Kconfig
[people/ms/u-boot.git] / include / configs / sandbox.h
CommitLineData
c861fbf7
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1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
1a459660 3 * SPDX-License-Identifier: GPL-2.0+
c861fbf7
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4 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
e2ee100f
SG
9#ifdef FTRACE
10#define CONFIG_TRACE
e2ee100f
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11#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
12#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
13#define CONFIG_TRACE_EARLY
14#define CONFIG_TRACE_EARLY_ADDR 0x00100000
15
16#endif
17
1c12bcee 18#ifndef CONFIG_SPL_BUILD
42d3b29d 19#define CONFIG_IO_TRACE
1c12bcee 20#endif
42d3b29d 21
9961a0b6 22#ifndef CONFIG_TIMER
28c860b2 23#define CONFIG_SYS_TIMER_RATE 1000000
9961a0b6 24#endif
28c860b2 25
7b06b66c
SG
26#define CONFIG_LMB
27
f4d8de48 28#define CONFIG_HOST_MAX_DEVICES 4
10fc1218 29
c861fbf7 30/*
b53e94b1 31 * Size of malloc() pool, before and after relocation
c861fbf7 32 */
b53e94b1 33#define CONFIG_MALLOC_F_ADDR 0x0010000
9f604425 34#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
c861fbf7 35
c861fbf7
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36#define CONFIG_SYS_LONGHELP /* #undef to save memory */
37#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
d63b5b4f 38#define CONFIG_DISPLAY_BOARDINFO_LATE
c861fbf7 39
c861fbf7
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40/* turn on command-line edit/c/auto */
41#define CONFIG_CMDLINE_EDITING
ed0fc4b1 42#define CONFIG_AUTO_COMPLETE
c861fbf7
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43
44#define CONFIG_ENV_SIZE 8192
c861fbf7 45
5e74934d 46/* SPI - enable all SPI flash types for testing purposes */
ca9a5019 47
ac395f08 48#define CONFIG_I2C_EDID
ac395f08 49
c861fbf7 50/* Memory things - we don't really want a memory test */
ecdbf419
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51#define CONFIG_SYS_LOAD_ADDR 0x00000000
52#define CONFIG_SYS_MEMTEST_START 0x00100000
c861fbf7 53#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000)
2c072c95
SG
54#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
55
56#define CONFIG_PHYSMEM
c861fbf7
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57
58/* Size of our emulated memory */
a733b06b 59#define CONFIG_SYS_SDRAM_BASE 0
c861fbf7 60#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
a733b06b
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61#define CONFIG_SYS_TEXT_BASE 0
62#define CONFIG_SYS_MONITOR_BASE 0
63#define CONFIG_NR_DRAM_BANKS 1
c861fbf7 64
c861fbf7
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65#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
66 115200}
c861fbf7 67
c861fbf7 68/* include default commands */
791a9f67
SS
69#include <config_distro_defaults.h>
70
71#define BOOT_TARGET_DEVICES(func) \
72 func(HOST, host, 1) \
73 func(HOST, host, 0)
74
75#include <config_distro_bootcmd.h>
c861fbf7 76
1f5bc524
JH
77#define CONFIG_KEEP_SERVERADDR
78#define CONFIG_UDP_CHECKSUM
1f5bc524 79#define CONFIG_TIMESTAMP
f3e0c374
JH
80#define CONFIG_BOOTP_DNS
81#define CONFIG_BOOTP_DNS2
f3e0c374
JH
82#define CONFIG_BOOTP_SEND_HOSTNAME
83#define CONFIG_BOOTP_SERVERIP
f3e0c374 84#define CONFIG_IP_DEFRAG
c861fbf7 85
ad0e4639 86#ifndef SANDBOX_NO_SDL
2c072c95 87#define CONFIG_SANDBOX_SDL
ad0e4639
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88#endif
89
90/* LCD and keyboard require SDL support */
91#ifdef CONFIG_SANDBOX_SDL
2c072c95 92#define LCD_BPP LCD_COLOR16
0156444c 93#define CONFIG_LCD_BMP_RLE8
747440d0
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94#define CONFIG_VIDEO_BMP_RLE8
95#define CONFIG_SPLASH_SCREEN_ALIGN
2c072c95 96
ad0e4639
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97#define CONFIG_KEYBOARD
98
460a7172 99#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
f1a1247d
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100 "stdout=serial,vidconsole\0" \
101 "stderr=serial,vidconsole\0"
ad0e4639 102#else
3ea143ab 103#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
f1a1247d
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104 "stdout=serial,vidconsole\0" \
105 "stderr=serial,vidconsole\0"
ad0e4639 106#endif
c861fbf7 107
3ea143ab
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108#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
109 "eth1addr=00:00:11:22:33:45\0" \
71d7971f
BM
110 "eth3addr=00:00:11:22:33:46\0" \
111 "eth5addr=00:00:11:22:33:47\0" \
3ea143ab
JH
112 "ipaddr=1.2.3.4\0"
113
791a9f67
SS
114#define MEM_LAYOUT_ENV_SETTINGS \
115 "bootm_size=0x10000000\0" \
116 "kernel_addr_r=0x1000000\0" \
117 "fdt_addr_r=0xc00000\0" \
118 "ramdisk_addr_r=0x2000000\0" \
119 "scriptaddr=0x1000\0" \
120 "pxefile_addr_r=0x2000\0"
121
122#define CONFIG_EXTRA_ENV_SETTINGS \
123 SANDBOX_SERIAL_SETTINGS \
124 SANDBOX_ETH_SETTINGS \
125 BOOTENV \
126 MEM_LAYOUT_ENV_SETTINGS
3ea143ab 127
3153e915
KC
128#define CONFIG_GZIP_COMPRESSED
129#define CONFIG_BZIP2
3153e915 130
1c12bcee 131#ifndef CONFIG_SPL_BUILD
74c6dc14
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132#define CONFIG_SYS_IDE_MAXBUS 1
133#define CONFIG_SYS_ATA_IDE0_OFFSET 0
134#define CONFIG_SYS_IDE_MAXDEVICE 2
135#define CONFIG_SYS_ATA_BASE_ADDR 0x100
136#define CONFIG_SYS_ATA_DATA_OFFSET 0
137#define CONFIG_SYS_ATA_REG_OFFSET 1
138#define CONFIG_SYS_ATA_ALT_OFFSET 2
139#define CONFIG_SYS_ATA_STRIDE 4
1c12bcee 140#endif
74c6dc14 141
e8c0a250
SG
142#define CONFIG_SCSI_AHCI_PLAT
143#define CONFIG_SYS_SCSI_MAX_DEVICE 2
144#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
145#define CONFIG_SYS_SCSI_MAX_LUN 4
146
199a1201
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147#define CONFIG_SYS_SATA_MAX_DEVICE 2
148
68969778
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149#define CONFIG_MISC_INIT_F
150
c861fbf7 151#endif