[people/ms/u-boot.git] / include / configs / sbc405.h

/*
 * (C) Copyright 2001
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_SBC405		1	/* ...on a WR SBC405 board	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/

#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600

#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"

#define CONFIG_RAMBOOT								\
	"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
	"bootm ffc00000 ffca0000"
#define CONFIG_NFSBOOT								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
	"bootm ffc00000"

#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND      "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx"      /* autoboot command     */


#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this	*/

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
		"e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
		"f=0x08 tn=sbc405 o=emac \0" \
	"env_startaddr=FF000000\0" \
	"env_endaddr=FF03FFFF\0" \
	"loadfile=vxWorks.st\0" \
	"loadaddr=0x01000000\0" \
	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
	"uboot_startaddr=FFFC0000\0" \
	"uboot_endaddr=FFFFFFFF\0" \
	"update=tftp ${loadaddr} u-boot.bin;" \
		"protect off ${uboot_startaddr} ${uboot_endaddr};" \
		"era ${uboot_startaddr} ${uboot_endaddr};" \
		"cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
		"protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
	"zapenv=protect off ${env_startaddr} ${env_endaddr};" \
		"era ${env_startaddr} ${env_endaddr};" \
		"protect on ${env_startaddr} ${env_endaddr}\0"

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


#define CONFIG_ENV_OVERWRITE


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_BSP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SDRAM


#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

#define CONFIG_ETHADDR	DE:AD:BE:EF:01:01	/* Ethernet address	*/
#define CONFIG_IPADDR		192.168.193.102
#define CONFIG_NETMASK		255.255.255.224
#define CONFIG_SERVERIP		192.168.193.119
#define CONFIG_GATEWAYIP	192.168.193.97

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_serial_clock()

#undef CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
#define CONFIG_SYS_BASE_BAUD		691200

/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE					\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,	\
	 57600, 115200, 230400, 460800, 921600 }

#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_info (bd_t) */

#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_VERSION_VARIABLE	1	/* include version env variable */

#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */

#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
#undef  CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER	0	/* configure as pci adapter	*/
#define PCI_HOST_FORCE		1	/* configure as pci host	*/
#define PCI_HOST_AUTO		2	/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE	/* select pci host function	*/
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
					/* resource configuration	*/

#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID	0x0408	/* PCI Device ID: PMC-405	*/
#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI	0x00000000	/* Host: use this pci address	*/
#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CONFIG_SYS_PCI_PTM2PCI	0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_MONITOR_BASE	0xFFFC0000
#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant		*/
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Flash Erase Timeout (in ms)		*/
#define CONFIG_SYS_FLASH_INCREMENT	0x01000000
#undef CONFIG_SYS_FLASH_PROTECTION		/* don't use hardware protection	*/
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)		*/
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

/*-----------------------------------------------------------------------
 * Environment Variable setup
 */
#define CONFIG_ENV_ADDR	CONFIG_SYS_FLASH_BASE	/* starting right at the beginning	*/
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0	/* starting right at the beginning	*/
#define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
#define CONFIG_ENV_SIZE		0x40000	/* Total Size of Environment Sector	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */
#define FLASH0_BA	CONFIG_SYS_FLASH_BASE		/* FLASH 0 Base Address		*/

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CONFIG_SYS_EBC_PB0AP	0x92015480
#define CONFIG_SYS_EBC_PB0CR	FLASH0_BA | 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM	1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 */
#define SPD_EEPROM_ADDRESS	0x50
#define CONFIG_SPD_EEPROM	1	/* use SPD EEPROM for setup		*/

#endif	/* __CONFIG_H */
Commit	Line	Data
652a10c0 WD	1	/*
	2	* (C) Copyright 2001
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
652a10c0 WD	5	*/
	6
	7	/*
	8	* board/config.h - configuration options, board specific
	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/*
	15	* High Level Configuration Options
	16	* (easy to change)
	17	*/
	18
	19	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	20	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	21	#define CONFIG_SBC405 1 /* ...on a WR SBC405 board */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	24
652a10c0 WD	25	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
	26	#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
	27
	28	#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
	29
	30	#define CONFIG_BAUDRATE 9600
	31
	32	#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot for the sbc405;echo;echo Type \"? or help\" to get on-line help;echo"
	33
	34	#define CONFIG_RAMBOOT \
fe126d8b WD	35	"setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	36	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
652a10c0 WD	37	"bootm ffc00000 ffca0000"
652a10c0 WD	38	#define CONFIG_NFSBOOT \
fe126d8b WD	39	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	40	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
652a10c0 WD	41	"bootm ffc00000"
	42
	43	#undef CONFIG_BOOTARGS
fe126d8b	44	#define CONFIG_BOOTCOMMAND "version;echo;tftpboot ${loadaddr} ${loadfile};bootvx" /* autoboot command */
652a10c0 WD	45
652a10c0 WD	46
96e21f86	47	#define CONFIG_PPC4xx_EMAC
652a10c0 WD	48	#define CONFIG_MII 1 /* MII PHY management */
	49	#define CONFIG_PHY_ADDR 0 /* PHY address */
	50	#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */
	51
	52	#define CONFIG_EXTRA_ENV_SETTINGS \
	53	"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
	54	"e=192.168.193.102:ffffffe0 h=192.168.193.100 u=target pw=hello " \
	55	"f=0x08 tn=sbc405 o=emac \0" \
	56	"env_startaddr=FF000000\0" \
	57	"env_endaddr=FF03FFFF\0" \
	58	"loadfile=vxWorks.st\0" \
	59	"loadaddr=0x01000000\0" \
fe126d8b	60	"net_load=tftpboot ${loadaddr} ${loadfile}\0" \
652a10c0 WD	61	"uboot_startaddr=FFFC0000\0" \
652a10c0 WD	62	"uboot_endaddr=FFFFFFFF\0" \
fe126d8b WD	63	"update=tftp ${loadaddr} u-boot.bin;" \
	64	"protect off ${uboot_startaddr} ${uboot_endaddr};" \
	65	"era ${uboot_startaddr} ${uboot_endaddr};" \
	66	"cp.b ${loadaddr} ${uboot_startaddr} ${filesize};" \
	67	"protect on ${uboot_startaddr} ${uboot_endaddr}\0" \
	68	"zapenv=protect off ${env_startaddr} ${env_endaddr};" \
	69	"era ${env_startaddr} ${env_endaddr};" \
	70	"protect on ${env_startaddr} ${env_endaddr}\0"
652a10c0 WD	71
	72	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	73
d3b8c1a7 JL	74	/*
	75	* BOOTP options
	76	*/
	77	#define CONFIG_BOOTP_SUBNETMASK
	78	#define CONFIG_BOOTP_GATEWAY
	79	#define CONFIG_BOOTP_HOSTNAME
	80	#define CONFIG_BOOTP_BOOTPATH
	81	#define CONFIG_BOOTP_BOOTFILESIZE
	82
652a10c0 WD	83
	84	#define CONFIG_ENV_OVERWRITE
	85
866e3089 JL	86
	87	/*
	88	* Command line configuration.
	89	*/
	90	#include <config_cmd_default.h>
	91
	92	#define CONFIG_CMD_BSP
	93	#define CONFIG_CMD_ELF
	94	#define CONFIG_CMD_I2C
	95	#define CONFIG_CMD_IRQ
	96	#define CONFIG_CMD_MII
	97	#define CONFIG_CMD_PCI
	98	#define CONFIG_CMD_PING
	99	#define CONFIG_CMD_SDRAM
	100
652a10c0 WD	101
	102	#undef CONFIG_WATCHDOG /* watchdog disabled */
	103
	104	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	105
	106	#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
	107	#define CONFIG_IPADDR 192.168.193.102
	108	#define CONFIG_NETMASK 255.255.255.224
	109	#define CONFIG_SERVERIP 192.168.193.119
	110	#define CONFIG_GATEWAYIP 192.168.193.97
	111
	112	/*
	113	* Miscellaneous configurable options
	114	*/
6d0f6bcf JCPV	115	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	116	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
652a10c0	117
6d0f6bcf	118	#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
652a10c0	119
866e3089	120	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	121	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
652a10c0	122	#else
6d0f6bcf	123	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
652a10c0	124	#endif
6d0f6bcf JCPV	125	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	126	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	127	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
652a10c0	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	130	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
652a10c0	131
550650dd SR	132	#define CONFIG_CONS_INDEX 1 /* Use UART0 */
	133	#define CONFIG_SYS_NS16550
	134	#define CONFIG_SYS_NS16550_SERIAL
	135	#define CONFIG_SYS_NS16550_REG_SIZE 1
	136	#define CONFIG_SYS_NS16550_CLK get_serial_clock()
	137
6d0f6bcf	138	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
6d0f6bcf	139	#define CONFIG_SYS_BASE_BAUD 691200
652a10c0 WD	140
652a10c0 WD	141	/* The following table includes the supported baudrates */
6d0f6bcf	142	#define CONFIG_SYS_BAUDRATE_TABLE \
652a10c0 WD	143	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	144	57600, 115200, 230400, 460800, 921600 }
	145
6d0f6bcf JCPV	146	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6d0f6bcf JCPV	147	#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
652a10c0	148
6d0f6bcf	149	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
652a10c0 WD	150
	151	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
	152
6d0f6bcf	153	#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
652a10c0 WD	154
	155	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	156	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
d0b0dcaa	157	#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
6d0f6bcf JCPV	158	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	159	#define CONFIG_SYS_I2C_SLAVE 0x7F
652a10c0 WD	160
	161	/*-----------------------------------------------------------------------
	162	* PCI stuff
	163	*-----------------------------------------------------------------------
	164	*/
	165	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	166	#define PCI_HOST_FORCE 1 /* configure as pci host */
	167	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	168
	169	#define CONFIG_PCI /* include pci support */
842033e6	170	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
652a10c0 WD	171	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	172	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	173	/* resource configuration */
	174
	175	#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	178	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
	179	#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	180	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	181	#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	182	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	183	#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
	184	#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	185	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
652a10c0 WD	186
	187	/*-----------------------------------------------------------------------
	188	* Start addresses for the final memory configuration
	189	* (Set up by the startup code)
6d0f6bcf	190	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
652a10c0	191	*/
6d0f6bcf JCPV	192	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	193	#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
	194	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
	195	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
652a10c0 WD	196
	197	/*
	198	* For booting Linux, the board info and command line data
	199	* have to be in the first 8 MB of memory, since this is
	200	* the maximum mapped by the Linux kernel during initialization.
	201	*/
6d0f6bcf	202	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
652a10c0 WD	203
	204	/*-----------------------------------------------------------------------
	205	* FLASH organization
	206	*/
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_BASE 0xFF000000
	208	#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
	209	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
	210	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
	211	#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
	212	#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
	213	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
	214	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	215	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	216	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
652a10c0 WD	217
	218	/*-----------------------------------------------------------------------
	219	* Environment Variable setup
	220	*/
6d0f6bcf	221	#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* starting right at the beginning */
5a1aceb0	222	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	223	#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
	224	#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
	225	#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
652a10c0	226
652a10c0 WD	227	/*-----------------------------------------------------------------------
	228	* External Bus Controller (EBC) Setup
	229	*/
6d0f6bcf	230	#define FLASH0_BA CONFIG_SYS_FLASH_BASE /* FLASH 0 Base Address */
652a10c0 WD	231
652a10c0 WD	232	/* Memory Bank 0 (Flash Bank 0) initialization */
6d0f6bcf JCPV	233	#define CONFIG_SYS_EBC_PB0AP 0x92015480
6d0f6bcf JCPV	234	#define CONFIG_SYS_EBC_PB0CR FLASH0_BA \| 0x9C000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=32bit*/
652a10c0 WD	235
	236	/*-----------------------------------------------------------------------
	237	* Definitions for initial stack pointer and data area (in data cache)
	238	*/
	239
	240	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
6d0f6bcf	241	#define CONFIG_SYS_TEMP_STACK_OCM 1
652a10c0 WD	242
652a10c0 WD	243	/* On Chip Memory location */
6d0f6bcf JCPV	244	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	245	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	246
	247	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	248	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
25ddd1fb	249	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	250	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
652a10c0 WD	251
	252	/*-----------------------------------------------------------------------
	253	* Definitions for Serial Presence Detect EEPROM address
	254	* (to get SDRAM settings)
	255	*/
	256	#define SPD_EEPROM_ADDRESS 0x50
	257	#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
	258
652a10c0	259	#endif /* __CONFIG_H */