projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 91e25769 PG |
1 | /* |
| 2 | * WindRiver SBC8349 U-Boot configuration file. | |
| 3 | * Copyright (c) 2006, 2007 Wind River Systems, Inc. | |
| 4 | * | |
| 5 | * Paul Gortmaker <paul.gortmaker@windriver.com> | |
| 6 | * Based on the MPC8349EMDS config. | |
| 7 | * | |
| 8 | * See file CREDITS for list of people who contributed to this | |
| 9 | * project. | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of | |
| 14 | * the License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This program is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * You should have received a copy of the GNU General Public License | |
| 22 | * along with this program; if not, write to the Free Software | |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 24 | * MA 02111-1307 USA | |
| 25 | */ | |
| 26 | ||
| 27 | /* | |
| 28 | * sbc8349 board configuration file. | |
| 29 | */ | |
| 30 | ||
| 31 | #ifndef __CONFIG_H | |
| 32 | #define __CONFIG_H | |
| 33 | ||
| 00ec0ff5 PG |
34 | /* |
| 35 | * Top level Makefile configuration choices | |
| 36 | */ | |
| 37 | #ifdef CONFIG_MK_PCI | |
| 38 | #define CONFIG_PCI | |
| 39 | #endif | |
| 40 | ||
| 41 | #ifdef CONFIG_MK_66 | |
| 42 | #define PCI_66M | |
| 43 | #endif | |
| 44 | ||
| 45 | #ifdef CONFIG_MK_33 | |
| 46 | #define PCI_33M | |
| 47 | #endif | |
| 48 | ||
| 91e25769 PG |
49 | /* |
| 50 | * High Level Configuration Options | |
| 51 | */ | |
| 52 | #define CONFIG_E300 1 /* E300 Family */ | |
| 0f898604 | 53 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ |
| 2c7920af | 54 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
| 91e25769 PG |
55 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
| 56 | #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ | |
| 57 | ||
| 91e25769 PG |
58 | /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ |
| 59 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ | |
| 60 | ||
| c0d660fb PG |
61 | /* |
| 62 | * The default if PCI isn't enabled, or if no PCI clk setting is given | |
| 63 | * is 66MHz; this is what the board defaults to when the PCI slot is | |
| 64 | * physically empty. The board will automatically (i.e w/o jumpers) | |
| 65 | * clock down to 33MHz if you insert a 33MHz PCI card. | |
| 66 | */ | |
| 67 | #ifdef PCI_33M | |
| 91e25769 | 68 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ |
| c0d660fb PG |
69 | #else /* 66M */ |
| 70 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
| 91e25769 PG |
71 | #endif |
| 72 | ||
| 73 | #ifndef CONFIG_SYS_CLK_FREQ | |
| c0d660fb | 74 | #ifdef PCI_33M |
| 91e25769 PG |
75 | #define CONFIG_SYS_CLK_FREQ 33000000 |
| 76 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 | |
| c0d660fb PG |
77 | #else /* 66M */ |
| 78 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
| 79 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 | |
| 91e25769 PG |
80 | #endif |
| 81 | #endif | |
| 82 | ||
| 91e25769 PG |
83 | #undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
| 84 | ||
| 6d0f6bcf | 85 | #define CONFIG_SYS_IMMR 0xE0000000 |
| 91e25769 | 86 | |
| 6d0f6bcf JCPV |
87 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 88 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ | |
| 89 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
| 91e25769 PG |
90 | |
| 91 | /* | |
| 92 | * DDR Setup | |
| 93 | */ | |
| 94 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 95 | #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ | |
| 96 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ | |
| 6d0f6bcf | 97 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ |
| 91e25769 PG |
98 | |
| 99 | /* | |
| 100 | * 32-bit data path mode. | |
| 101 | * | |
| 102 | * Please note that using this mode for devices with the real density of 64-bit | |
| 103 | * effectively reduces the amount of available memory due to the effect of | |
| 104 | * wrapping around while translating address to row/columns, for example in the | |
| 105 | * 256MB module the upper 128MB get aliased with contents of the lower | |
| 106 | * 128MB); normally this define should be used for devices with real 32-bit | |
| 107 | * data path. | |
| 108 | */ | |
| 109 | #undef CONFIG_DDR_32BIT | |
| 110 | ||
| 6d0f6bcf JCPV |
111 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 112 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 113 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 114 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
| 91e25769 PG |
115 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
| 116 | #define CONFIG_DDR_2T_TIMING | |
| 117 | ||
| 118 | #if defined(CONFIG_SPD_EEPROM) | |
| 119 | /* | |
| 120 | * Determine DDR configuration from I2C interface. | |
| 121 | */ | |
| 122 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ | |
| 123 | ||
| 124 | #else | |
| 125 | /* | |
| 126 | * Manually set up DDR parameters | |
| 127 | * NB: manual DDR setup untested on sbc834x | |
| 128 | */ | |
| 6d0f6bcf JCPV |
129 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
| 130 | #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) | |
| 131 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 | |
| 132 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
| 133 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ | |
| 134 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ | |
| 91e25769 PG |
135 | |
| 136 | #if defined(CONFIG_DDR_32BIT) | |
| 137 | /* set burst length to 8 for 32-bit data path */ | |
| 6d0f6bcf | 138 | #define CONFIG_SYS_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ |
| 91e25769 PG |
139 | #else |
| 140 | /* the default burst length is 4 - for 64-bit data path */ | |
| 6d0f6bcf | 141 | #define CONFIG_SYS_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ |
| 91e25769 PG |
142 | #endif |
| 143 | #endif | |
| 144 | ||
| 145 | /* | |
| 146 | * SDRAM on the Local Bus | |
| 147 | */ | |
| 6d0f6bcf JCPV |
148 | #define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ |
| 149 | #define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ | |
| 91e25769 PG |
150 | |
| 151 | /* | |
| 152 | * FLASH on the Local Bus | |
| 153 | */ | |
| 6d0f6bcf | 154 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 00b1883a | 155 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
| 6d0f6bcf JCPV |
156 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
| 157 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ | |
| 158 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
| 91e25769 | 159 | |
| 6d0f6bcf | 160 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ |
| 91e25769 PG |
161 | (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ |
| 162 | BR_V) /* valid */ | |
| 163 | ||
| 6d0f6bcf JCPV |
164 | #define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ |
| 165 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ | |
| 166 | #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ | |
| 91e25769 | 167 | |
| 6d0f6bcf JCPV |
168 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 169 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
| 91e25769 | 170 | |
| 6d0f6bcf JCPV |
171 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 172 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 173 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 91e25769 | 174 | |
| 6d0f6bcf | 175 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 91e25769 | 176 | |
| 6d0f6bcf JCPV |
177 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 178 | #define CONFIG_SYS_RAMBOOT | |
| 91e25769 | 179 | #else |
| 6d0f6bcf | 180 | #undef CONFIG_SYS_RAMBOOT |
| 91e25769 PG |
181 | #endif |
| 182 | ||
| 6d0f6bcf JCPV |
183 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 184 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
| 185 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
| 91e25769 | 186 | |
| 6d0f6bcf JCPV |
187 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
| 188 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 189 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
| 91e25769 | 190 | |
| 6d0f6bcf JCPV |
191 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 192 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 91e25769 PG |
193 | |
| 194 | /* | |
| 195 | * Local Bus LCRR and LBCR regs | |
| 196 | * LCRR: DLL bypass, Clock divider is 4 | |
| 197 | * External Local Bus rate is | |
| 198 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 199 | */ | |
| 6d0f6bcf JCPV |
200 | #define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
| 201 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
| 91e25769 | 202 | |
| 6d0f6bcf | 203 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ |
| 91e25769 | 204 | |
| 6d0f6bcf | 205 | #ifdef CONFIG_SYS_LB_SDRAM |
| 91e25769 PG |
206 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ |
| 207 | /* | |
| 208 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 6d0f6bcf | 209 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 91e25769 PG |
210 | * |
| 211 | * For BR2, need: | |
| 212 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 213 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 214 | * no parity checking = BR2[21:22] = 00 | |
| 215 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 216 | * Valid = BR[31] = 1 | |
| 217 | * | |
| 218 | * 0 4 8 12 16 20 24 28 | |
| 219 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
| 220 | * | |
| 6d0f6bcf | 221 | * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into |
| 91e25769 PG |
222 | * FIXME: the top 17 bits of BR2. |
| 223 | */ | |
| 224 | ||
| 6d0f6bcf JCPV |
225 | #define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ |
| 226 | #define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 | |
| 227 | #define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ | |
| 91e25769 PG |
228 | |
| 229 | /* | |
| 6d0f6bcf | 230 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 91e25769 PG |
231 | * |
| 232 | * For OR2, need: | |
| 233 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 234 | * XAM, OR2[17:18] = 11 | |
| 235 | * 9 columns OR2[19-21] = 010 | |
| 236 | * 13 rows OR2[23-25] = 100 | |
| 237 | * EAD set for extra time OR[31] = 1 | |
| 238 | * | |
| 239 | * 0 4 8 12 16 20 24 28 | |
| 240 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
| 241 | */ | |
| 242 | ||
| 6d0f6bcf | 243 | #define CONFIG_SYS_OR2_PRELIM 0xFC006901 |
| 91e25769 | 244 | |
| 6d0f6bcf JCPV |
245 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
| 246 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ | |
| 91e25769 | 247 | |
| 540dcf1c KG |
248 | #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ |
| 249 | | LSDMR_BSMA1516 \ | |
| 250 | | LSDMR_RFCR8 \ | |
| 251 | | LSDMR_PRETOACT6 \ | |
| 252 | | LSDMR_ACTTORW3 \ | |
| 253 | | LSDMR_BL8 \ | |
| 254 | | LSDMR_WRC3 \ | |
| 255 | | LSDMR_CL3 \ | |
| 91e25769 PG |
256 | ) |
| 257 | ||
| 258 | /* | |
| 259 | * SDRAM Controller configuration sequence. | |
| 260 | */ | |
| 540dcf1c KG |
261 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 262 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 263 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 264 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
| 265 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
| 91e25769 PG |
266 | #endif |
| 267 | ||
| 268 | /* | |
| 269 | * Serial Port | |
| 270 | */ | |
| 271 | #define CONFIG_CONS_INDEX 1 | |
| 272 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 6d0f6bcf JCPV |
273 | #define CONFIG_SYS_NS16550 |
| 274 | #define CONFIG_SYS_NS16550_SERIAL | |
| 275 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 276 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 91e25769 | 277 | |
| 6d0f6bcf | 278 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 91e25769 PG |
279 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 280 | ||
| 6d0f6bcf JCPV |
281 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 282 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 91e25769 | 283 | |
| 22d71a71 | 284 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 91e25769 | 285 | /* Use the HUSH parser */ |
| 6d0f6bcf JCPV |
286 | #define CONFIG_SYS_HUSH_PARSER |
| 287 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 288 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 91e25769 PG |
289 | #endif |
| 290 | ||
| 291 | /* pass open firmware flat tree */ | |
| e496865e | 292 | #define CONFIG_OF_LIBFDT 1 |
| 91e25769 | 293 | #define CONFIG_OF_BOARD_SETUP 1 |
| 5b8bc606 | 294 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 91e25769 PG |
295 | |
| 296 | /* I2C */ | |
| 297 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| 298 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 299 | #define CONFIG_FSL_I2C | |
| 6d0f6bcf JCPV |
300 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 301 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 302 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 303 | #define CONFIG_SYS_I2C1_OFFSET 0x3000 | |
| 304 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 305 | #define CONFIG_SYS_I2C_OFFSET CONFIG_SYS_I2C2_OFFSET | |
| 91e25769 PG |
306 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ |
| 307 | ||
| 308 | /* TSEC */ | |
| 6d0f6bcf JCPV |
309 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| 310 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
| 311 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 | |
| 312 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
| 91e25769 PG |
313 | |
| 314 | /* | |
| 315 | * General PCI | |
| 316 | * Addresses are mapped 1-1. | |
| 317 | */ | |
| 6d0f6bcf JCPV |
318 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 319 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 320 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 321 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 322 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 323 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 324 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
| 325 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 326 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 327 | ||
| 328 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
| 329 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
| 330 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 331 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
| 332 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
| 333 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 334 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
| 335 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
| 336 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 91e25769 PG |
337 | |
| 338 | #if defined(CONFIG_PCI) | |
| 339 | ||
| 340 | #define PCI_64BIT | |
| 341 | #define PCI_ONE_PCI1 | |
| 342 | #if defined(PCI_64BIT) | |
| 343 | #undef PCI_ALL_PCI1 | |
| 344 | #undef PCI_TWO_PCI1 | |
| 345 | #undef PCI_ONE_PCI1 | |
| 346 | #endif | |
| 347 | ||
| 348 | #define CONFIG_NET_MULTI | |
| 349 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 350 | ||
| 351 | #undef CONFIG_EEPRO100 | |
| 352 | #undef CONFIG_TULIP | |
| 353 | ||
| 354 | #if !defined(CONFIG_PCI_PNP) | |
| 355 | #define PCI_ENET0_IOADDR 0xFIXME | |
| 356 | #define PCI_ENET0_MEMADDR 0xFIXME | |
| 357 | #define PCI_IDSEL_NUMBER 0xFIXME | |
| 358 | #endif | |
| 359 | ||
| 360 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 361 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| 91e25769 PG |
362 | |
| 363 | #endif /* CONFIG_PCI */ | |
| 364 | ||
| 365 | /* | |
| 366 | * TSEC configuration | |
| 367 | */ | |
| 368 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
| 369 | ||
| 370 | #if defined(CONFIG_TSEC_ENET) | |
| 371 | #ifndef CONFIG_NET_MULTI | |
| 372 | #define CONFIG_NET_MULTI 1 | |
| 373 | #endif | |
| 374 | ||
| 255a3577 KP |
375 | #define CONFIG_TSEC1 1 |
| 376 | #define CONFIG_TSEC1_NAME "TSEC0" | |
| 377 | #define CONFIG_TSEC2 1 | |
| 378 | #define CONFIG_TSEC2_NAME "TSEC1" | |
| 91e25769 PG |
379 | #define CONFIG_PHY_BCM5421S 1 |
| 380 | #define TSEC1_PHY_ADDR 0x19 | |
| 381 | #define TSEC2_PHY_ADDR 0x1a | |
| 382 | #define TSEC1_PHYIDX 0 | |
| 383 | #define TSEC2_PHYIDX 0 | |
| 3a79013e AF |
384 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 385 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 91e25769 PG |
386 | |
| 387 | /* Options are: TSEC[0-1] */ | |
| 388 | #define CONFIG_ETHPRIME "TSEC0" | |
| 389 | ||
| 390 | #endif /* CONFIG_TSEC_ENET */ | |
| 391 | ||
| 392 | /* | |
| 393 | * Environment | |
| 394 | */ | |
| 6d0f6bcf | 395 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 396 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 397 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| 0e8d1586 JCPV |
398 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 399 | #define CONFIG_ENV_SIZE 0x2000 | |
| 91e25769 PG |
400 | |
| 401 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
402 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 403 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 91e25769 PG |
404 | |
| 405 | #else | |
| 6d0f6bcf | 406 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
| 93f6d725 | 407 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 408 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 0e8d1586 | 409 | #define CONFIG_ENV_SIZE 0x2000 |
| 91e25769 PG |
410 | #endif |
| 411 | ||
| 412 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 413 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 91e25769 | 414 | |
| 866e3089 | 415 | |
| 079a136c JL |
416 | /* |
| 417 | * BOOTP options | |
| 418 | */ | |
| 419 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 420 | #define CONFIG_BOOTP_BOOTPATH | |
| 421 | #define CONFIG_BOOTP_GATEWAY | |
| 422 | #define CONFIG_BOOTP_HOSTNAME | |
| 423 | ||
| 424 | ||
| 866e3089 JL |
425 | /* |
| 426 | * Command line configuration. | |
| 427 | */ | |
| 428 | #include <config_cmd_default.h> | |
| 429 | ||
| 430 | #define CONFIG_CMD_I2C | |
| 431 | #define CONFIG_CMD_MII | |
| 432 | #define CONFIG_CMD_PING | |
| 433 | ||
| 91e25769 | 434 | #if defined(CONFIG_PCI) |
| e496865e | 435 | #define CONFIG_CMD_PCI |
| 91e25769 | 436 | #endif |
| 866e3089 | 437 | |
| 6d0f6bcf | 438 | #if defined(CONFIG_SYS_RAMBOOT) |
| bdab39d3 | 439 | #undef CONFIG_CMD_SAVEENV |
| 866e3089 | 440 | #undef CONFIG_CMD_LOADS |
| 91e25769 PG |
441 | #endif |
| 442 | ||
| 91e25769 PG |
443 | |
| 444 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 445 | ||
| 446 | /* | |
| 447 | * Miscellaneous configurable options | |
| 448 | */ | |
| 6d0f6bcf JCPV |
449 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 450 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 451 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 91e25769 | 452 | |
| 866e3089 | 453 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 454 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 91e25769 | 455 | #else |
| 6d0f6bcf | 456 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 91e25769 PG |
457 | #endif |
| 458 | ||
| 6d0f6bcf JCPV |
459 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 460 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 461 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 462 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 91e25769 PG |
463 | |
| 464 | /* | |
| 465 | * For booting Linux, the board info and command line data | |
| 466 | * have to be in the first 8 MB of memory, since this is | |
| 467 | * the maximum mapped by the Linux kernel during initialization. | |
| 468 | */ | |
| 6d0f6bcf | 469 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 91e25769 | 470 | |
| 6d0f6bcf | 471 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
| 91e25769 PG |
472 | |
| 473 | #if 1 /*528/264*/ | |
| 6d0f6bcf | 474 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
475 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 476 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 477 | HRCWL_CSB_TO_CLKIN |\ | |
| 478 | HRCWL_VCO_1X2 |\ | |
| 479 | HRCWL_CORE_TO_CSB_2X1) | |
| 480 | #elif 0 /*396/132*/ | |
| 6d0f6bcf | 481 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
482 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 483 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 484 | HRCWL_CSB_TO_CLKIN |\ | |
| 485 | HRCWL_VCO_1X4 |\ | |
| 486 | HRCWL_CORE_TO_CSB_3X1) | |
| 487 | #elif 0 /*264/132*/ | |
| 6d0f6bcf | 488 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
489 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 490 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 491 | HRCWL_CSB_TO_CLKIN |\ | |
| 492 | HRCWL_VCO_1X4 |\ | |
| 493 | HRCWL_CORE_TO_CSB_2X1) | |
| 494 | #elif 0 /*132/132*/ | |
| 6d0f6bcf | 495 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
496 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 497 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 498 | HRCWL_CSB_TO_CLKIN |\ | |
| 499 | HRCWL_VCO_1X4 |\ | |
| 500 | HRCWL_CORE_TO_CSB_1X1) | |
| 501 | #elif 0 /*264/264 */ | |
| 6d0f6bcf | 502 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
503 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 504 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 505 | HRCWL_CSB_TO_CLKIN |\ | |
| 506 | HRCWL_VCO_1X4 |\ | |
| 507 | HRCWL_CORE_TO_CSB_1X1) | |
| 508 | #endif | |
| 509 | ||
| 510 | #if defined(PCI_64BIT) | |
| 6d0f6bcf | 511 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 91e25769 PG |
512 | HRCWH_PCI_HOST |\ |
| 513 | HRCWH_64_BIT_PCI |\ | |
| 514 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 515 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 516 | HRCWH_CORE_ENABLE |\ | |
| 517 | HRCWH_FROM_0X00000100 |\ | |
| 518 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 519 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 520 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 521 | HRCWH_TSEC1M_IN_GMII |\ | |
| 522 | HRCWH_TSEC2M_IN_GMII ) | |
| 523 | #else | |
| 6d0f6bcf | 524 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 91e25769 PG |
525 | HRCWH_PCI_HOST |\ |
| 526 | HRCWH_32_BIT_PCI |\ | |
| 527 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 528 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
| 529 | HRCWH_CORE_ENABLE |\ | |
| 530 | HRCWH_FROM_0X00000100 |\ | |
| 531 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 532 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 533 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 534 | HRCWH_TSEC1M_IN_GMII |\ | |
| 535 | HRCWH_TSEC2M_IN_GMII ) | |
| 536 | #endif | |
| 537 | ||
| 538 | /* System IO Config */ | |
| 3c9b1ee1 | 539 | #define CONFIG_SYS_SICRH 0 |
| 6d0f6bcf | 540 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
| 91e25769 | 541 | |
| 6d0f6bcf JCPV |
542 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 543 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
| 91e25769 | 544 | |
| 6d0f6bcf | 545 | /* #define CONFIG_SYS_HID0_FINAL (\ |
| 91e25769 PG |
546 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
| 547 | HID0_ENABLE_M_BIT |\ | |
| 548 | HID0_ENABLE_ADDRESS_BROADCAST ) */ | |
| 549 | ||
| 550 | ||
| 6d0f6bcf | 551 | #define CONFIG_SYS_HID2 HID2_HBE |
| 91e25769 | 552 | |
| 31d82672 BB |
553 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 554 | ||
| 91e25769 | 555 | /* DDR @ 0x00000000 */ |
| 6d0f6bcf JCPV |
556 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 557 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 91e25769 PG |
558 | |
| 559 | /* PCI @ 0x80000000 */ | |
| 560 | #ifdef CONFIG_PCI | |
| 6d0f6bcf JCPV |
561 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 562 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 563 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 564 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 91e25769 | 565 | #else |
| 6d0f6bcf JCPV |
566 | #define CONFIG_SYS_IBAT1L (0) |
| 567 | #define CONFIG_SYS_IBAT1U (0) | |
| 568 | #define CONFIG_SYS_IBAT2L (0) | |
| 569 | #define CONFIG_SYS_IBAT2U (0) | |
| 91e25769 PG |
570 | #endif |
| 571 | ||
| 572 | #ifdef CONFIG_MPC83XX_PCI2 | |
| 6d0f6bcf JCPV |
573 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
| 574 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 575 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 576 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 91e25769 | 577 | #else |
| 6d0f6bcf JCPV |
578 | #define CONFIG_SYS_IBAT3L (0) |
| 579 | #define CONFIG_SYS_IBAT3U (0) | |
| 580 | #define CONFIG_SYS_IBAT4L (0) | |
| 581 | #define CONFIG_SYS_IBAT4U (0) | |
| 91e25769 PG |
582 | #endif |
| 583 | ||
| 584 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
| 6d0f6bcf JCPV |
585 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 586 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 91e25769 PG |
587 | |
| 588 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
| c1230980 SW |
589 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ |
| 590 | BATL_GUARDEDSTORAGE) | |
| 6d0f6bcf JCPV |
591 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 592 | ||
| 593 | #define CONFIG_SYS_IBAT7L (0) | |
| 594 | #define CONFIG_SYS_IBAT7U (0) | |
| 595 | ||
| 596 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 597 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 598 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 599 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 600 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 601 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 602 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 603 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 604 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 605 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 606 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 607 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 608 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 609 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 610 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 611 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 91e25769 PG |
612 | |
| 613 | /* | |
| 614 | * Internal Definitions | |
| 615 | * | |
| 616 | * Boot Flags | |
| 617 | */ | |
| 618 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 619 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 620 | ||
| 866e3089 | 621 | #if defined(CONFIG_CMD_KGDB) |
| 91e25769 PG |
622 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 623 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 624 | #endif | |
| 625 | ||
| 626 | /* | |
| 627 | * Environment Configuration | |
| 628 | */ | |
| 629 | #define CONFIG_ENV_OVERWRITE | |
| 630 | ||
| 631 | #if defined(CONFIG_TSEC_ENET) | |
| 10327dc5 | 632 | #define CONFIG_HAS_ETH0 |
| 91e25769 PG |
633 | #define CONFIG_ETHADDR 00:a0:1e:a0:13:8d |
| 634 | #define CONFIG_HAS_ETH1 | |
| 635 | #define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e | |
| 636 | #endif | |
| 637 | ||
| 638 | #define CONFIG_IPADDR 192.168.1.234 | |
| 639 | ||
| 640 | #define CONFIG_HOSTNAME SBC8349 | |
| 641 | #define CONFIG_ROOTPATH /tftpboot/rootfs | |
| 642 | #define CONFIG_BOOTFILE uImage | |
| 643 | ||
| 644 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 645 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 646 | #define CONFIG_NETMASK 255.255.255.0 | |
| 647 | ||
| 79f516bc | 648 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
| 91e25769 PG |
649 | |
| 650 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
| 651 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 652 | ||
| 653 | #define CONFIG_BAUDRATE 115200 | |
| 654 | ||
| 655 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 656 | "netdev=eth0\0" \ | |
| a99715b8 | 657 | "hostname=sbc8349\0" \ |
| 91e25769 PG |
658 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 659 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 660 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 661 | "addip=setenv bootargs ${bootargs} " \ | |
| 662 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 663 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 664 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 665 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 666 | "bootm ${kernel_addr}\0" \ | |
| 667 | "flash_self=run ramargs addip addtty;" \ | |
| 668 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 669 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 670 | "bootm\0" \ | |
| 671 | "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ | |
| fe613cdd PG |
672 | "update=protect off ff800000 ff83ffff; " \ |
| 673 | "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ | |
| d8ab58b2 | 674 | "upd=run load update\0" \ |
| 79f516bc | 675 | "fdtaddr=780000\0" \ |
| a99715b8 | 676 | "fdtfile=sbc8349.dtb\0" \ |
| 91e25769 PG |
677 | "" |
| 678 | ||
| 679 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 680 | "setenv bootargs root=/dev/nfs rw " \ | |
| 681 | "nfsroot=$serverip:$rootpath " \ | |
| 682 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 683 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 684 | "tftp $loadaddr $bootfile;" \ | |
| 685 | "tftp $fdtaddr $fdtfile;" \ | |
| 686 | "bootm $loadaddr - $fdtaddr" | |
| 687 | ||
| 688 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 689 | "setenv bootargs root=/dev/ram rw " \ | |
| 690 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 691 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 692 | "tftp $loadaddr $bootfile;" \ | |
| 693 | "tftp $fdtaddr $fdtfile;" \ | |
| 694 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 695 | ||
| 696 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 697 | ||
| 698 | #endif /* __CONFIG_H */ |