projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 91e25769 PG |
1 | /* |
| 2 | * WindRiver SBC8349 U-Boot configuration file. | |
| 3 | * Copyright (c) 2006, 2007 Wind River Systems, Inc. | |
| 4 | * | |
| 5 | * Paul Gortmaker <paul.gortmaker@windriver.com> | |
| 6 | * Based on the MPC8349EMDS config. | |
| 7 | * | |
| 3765b3e7 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 91e25769 PG |
9 | */ |
| 10 | ||
| 11 | /* | |
| 12 | * sbc8349 board configuration file. | |
| 13 | */ | |
| 14 | ||
| 15 | #ifndef __CONFIG_H | |
| 16 | #define __CONFIG_H | |
| 17 | ||
| 91e25769 PG |
18 | /* |
| 19 | * High Level Configuration Options | |
| 20 | */ | |
| 21 | #define CONFIG_E300 1 /* E300 Family */ | |
| 2c7920af | 22 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
| 91e25769 PG |
23 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
| 24 | #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ | |
| 25 | ||
| 2ae18241 WD |
26 | #define CONFIG_SYS_TEXT_BASE 0xFF800000 |
| 27 | ||
| 91e25769 PG |
28 | /* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ |
| 29 | #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ | |
| 30 | ||
| c0d660fb PG |
31 | /* |
| 32 | * The default if PCI isn't enabled, or if no PCI clk setting is given | |
| 33 | * is 66MHz; this is what the board defaults to when the PCI slot is | |
| 34 | * physically empty. The board will automatically (i.e w/o jumpers) | |
| 35 | * clock down to 33MHz if you insert a 33MHz PCI card. | |
| 36 | */ | |
| 2ae18241 | 37 | #ifdef CONFIG_PCI_33M |
| 91e25769 | 38 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ |
| c0d660fb PG |
39 | #else /* 66M */ |
| 40 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
| 91e25769 PG |
41 | #endif |
| 42 | ||
| 43 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 2ae18241 | 44 | #ifdef CONFIG_PCI_33M |
| 91e25769 PG |
45 | #define CONFIG_SYS_CLK_FREQ 33000000 |
| 46 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 | |
| c0d660fb PG |
47 | #else /* 66M */ |
| 48 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
| 49 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 | |
| 91e25769 PG |
50 | #endif |
| 51 | #endif | |
| 52 | ||
| 6d0f6bcf | 53 | #define CONFIG_SYS_IMMR 0xE0000000 |
| 91e25769 | 54 | |
| 60e1dc15 | 55 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 6d0f6bcf JCPV |
56 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
| 57 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
| 91e25769 PG |
58 | |
| 59 | /* | |
| 60 | * DDR Setup | |
| 61 | */ | |
| 62 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 63 | #undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ | |
| 64 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ | |
| 60e1dc15 | 65 | #define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ |
| 91e25769 PG |
66 | |
| 67 | /* | |
| 68 | * 32-bit data path mode. | |
| 69 | * | |
| 70 | * Please note that using this mode for devices with the real density of 64-bit | |
| 71 | * effectively reduces the amount of available memory due to the effect of | |
| 72 | * wrapping around while translating address to row/columns, for example in the | |
| 73 | * 256MB module the upper 128MB get aliased with contents of the lower | |
| 74 | * 128MB); normally this define should be used for devices with real 32-bit | |
| 75 | * data path. | |
| 76 | */ | |
| 77 | #undef CONFIG_DDR_32BIT | |
| 78 | ||
| 60e1dc15 | 79 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
| 6d0f6bcf JCPV |
80 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE |
| 81 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| 82 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
| 91e25769 PG |
83 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
| 84 | #define CONFIG_DDR_2T_TIMING | |
| 85 | ||
| 86 | #if defined(CONFIG_SPD_EEPROM) | |
| 87 | /* | |
| 88 | * Determine DDR configuration from I2C interface. | |
| 89 | */ | |
| 90 | #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ | |
| 91 | ||
| 92 | #else | |
| 93 | /* | |
| 94 | * Manually set up DDR parameters | |
| 95 | * NB: manual DDR setup untested on sbc834x | |
| 96 | */ | |
| 6d0f6bcf | 97 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
| 2e651b24 | 98 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
| 60e1dc15 JH |
99 | | CSCONFIG_ROW_BIT_13 \ |
| 100 | | CSCONFIG_COL_BIT_10) | |
| 6d0f6bcf JCPV |
101 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
| 102 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
| 60e1dc15 | 103 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
| 6d0f6bcf | 104 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
| 91e25769 PG |
105 | |
| 106 | #if defined(CONFIG_DDR_32BIT) | |
| 107 | /* set burst length to 8 for 32-bit data path */ | |
| 60e1dc15 JH |
108 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
| 109 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
| 91e25769 PG |
110 | #else |
| 111 | /* the default burst length is 4 - for 64-bit data path */ | |
| 60e1dc15 JH |
112 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
| 113 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
| 91e25769 PG |
114 | #endif |
| 115 | #endif | |
| 116 | ||
| 117 | /* | |
| 118 | * SDRAM on the Local Bus | |
| 119 | */ | |
| 7d6a0982 JH |
120 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
| 121 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
| 91e25769 PG |
122 | |
| 123 | /* | |
| 124 | * FLASH on the Local Bus | |
| 125 | */ | |
| 60e1dc15 JH |
126 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
| 127 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 6d0f6bcf JCPV |
128 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ |
| 129 | #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ | |
| 130 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ | |
| 91e25769 | 131 | |
| 7d6a0982 JH |
132 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
| 133 | | BR_PS_16 /* 16 bit port */ \ | |
| 134 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
| 135 | | BR_V) /* valid */ | |
| 136 | ||
| 137 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
| 138 | | OR_GPCM_XAM \ | |
| 139 | | OR_GPCM_CSNT \ | |
| 140 | | OR_GPCM_ACS_DIV2 \ | |
| 141 | | OR_GPCM_XACS \ | |
| 142 | | OR_GPCM_SCY_15 \ | |
| 143 | | OR_GPCM_TRLX_SET \ | |
| 144 | | OR_GPCM_EHTR_SET \ | |
| 145 | | OR_GPCM_EAD) | |
| 146 | /* 0xFF806FF7 */ | |
| 91e25769 | 147 | |
| 60e1dc15 JH |
148 | /* window base at flash base */ |
| 149 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
| 7d6a0982 | 150 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) |
| 91e25769 | 151 | |
| 60e1dc15 JH |
152 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 153 | #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ | |
| 91e25769 | 154 | |
| 6d0f6bcf JCPV |
155 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 156 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 157 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 91e25769 | 158 | |
| 14d0a02a | 159 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 91e25769 | 160 | |
| 6d0f6bcf JCPV |
161 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 162 | #define CONFIG_SYS_RAMBOOT | |
| 91e25769 | 163 | #else |
| 6d0f6bcf | 164 | #undef CONFIG_SYS_RAMBOOT |
| 91e25769 PG |
165 | #endif |
| 166 | ||
| 6d0f6bcf | 167 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 60e1dc15 JH |
168 | /* Initial RAM address */ |
| 169 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 | |
| 170 | /* Size of used area in RAM*/ | |
| 171 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 | |
| 91e25769 | 172 | |
| 60e1dc15 JH |
173 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 174 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
| 6d0f6bcf | 175 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 91e25769 | 176 | |
| 60e1dc15 | 177 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| c8a90646 | 178 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
| 91e25769 PG |
179 | |
| 180 | /* | |
| 181 | * Local Bus LCRR and LBCR regs | |
| 182 | * LCRR: DLL bypass, Clock divider is 4 | |
| 183 | * External Local Bus rate is | |
| 184 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
| 185 | */ | |
| c7190f02 KP |
186 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
| 187 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
| 6d0f6bcf | 188 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
| 91e25769 | 189 | |
| 6d0f6bcf | 190 | #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ |
| 91e25769 | 191 | |
| 6d0f6bcf | 192 | #ifdef CONFIG_SYS_LB_SDRAM |
| 91e25769 PG |
193 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ |
| 194 | /* | |
| 195 | * Base Register 2 and Option Register 2 configure SDRAM. | |
| 6d0f6bcf | 196 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
| 91e25769 PG |
197 | * |
| 198 | * For BR2, need: | |
| 199 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
| 200 | * port-size = 32-bits = BR2[19:20] = 11 | |
| 201 | * no parity checking = BR2[21:22] = 00 | |
| 202 | * SDRAM for MSEL = BR2[24:26] = 011 | |
| 203 | * Valid = BR[31] = 1 | |
| 204 | * | |
| 205 | * 0 4 8 12 16 20 24 28 | |
| 206 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
| 91e25769 PG |
207 | */ |
| 208 | ||
| 7d6a0982 JH |
209 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
| 210 | | BR_PS_32 \ | |
| 211 | | BR_MS_SDRAM \ | |
| 212 | | BR_V) | |
| 213 | /* 0xF0001861 */ | |
| 214 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
| 215 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
| 91e25769 PG |
216 | |
| 217 | /* | |
| 6d0f6bcf | 218 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
| 91e25769 PG |
219 | * |
| 220 | * For OR2, need: | |
| 221 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
| 222 | * XAM, OR2[17:18] = 11 | |
| 223 | * 9 columns OR2[19-21] = 010 | |
| 224 | * 13 rows OR2[23-25] = 100 | |
| 225 | * EAD set for extra time OR[31] = 1 | |
| 226 | * | |
| 227 | * 0 4 8 12 16 20 24 28 | |
| 228 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
| 229 | */ | |
| 230 | ||
| 7d6a0982 JH |
231 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ |
| 232 | | OR_SDRAM_XAM \ | |
| 233 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
| 234 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
| 235 | | OR_SDRAM_EAD) | |
| 236 | /* 0xFC006901 */ | |
| 91e25769 | 237 | |
| 60e1dc15 JH |
238 | /* LB sdram refresh timer, about 6us */ |
| 239 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
| 240 | /* LB refresh timer prescal, 266MHz/32 */ | |
| 241 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
| 91e25769 | 242 | |
| 60e1dc15 JH |
243 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
| 244 | | LSDMR_BSMA1516 \ | |
| 245 | | LSDMR_RFCR8 \ | |
| 246 | | LSDMR_PRETOACT6 \ | |
| 247 | | LSDMR_ACTTORW3 \ | |
| 248 | | LSDMR_BL8 \ | |
| 249 | | LSDMR_WRC3 \ | |
| 250 | | LSDMR_CL3) | |
| 91e25769 PG |
251 | |
| 252 | /* | |
| 253 | * SDRAM Controller configuration sequence. | |
| 254 | */ | |
| 540dcf1c KG |
255 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
| 256 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 257 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
| 258 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
| 259 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
| 91e25769 PG |
260 | #endif |
| 261 | ||
| 262 | /* | |
| 263 | * Serial Port | |
| 264 | */ | |
| 265 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
266 | #define CONFIG_SYS_NS16550_SERIAL |
| 267 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 268 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 91e25769 | 269 | |
| 6d0f6bcf | 270 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 60e1dc15 | 271 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 91e25769 | 272 | |
| 6d0f6bcf JCPV |
273 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
| 274 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
| 91e25769 | 275 | |
| 22d71a71 | 276 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| a059e90e | 277 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 91e25769 | 278 | |
| 91e25769 | 279 | /* I2C */ |
| 00f792e0 HS |
280 | #define CONFIG_SYS_I2C |
| 281 | #define CONFIG_SYS_I2C_FSL | |
| 282 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 283 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 284 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
| 285 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
| 286 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
| 287 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
| 288 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } | |
| efaf6f1b | 289 | /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ |
| 91e25769 PG |
290 | |
| 291 | /* TSEC */ | |
| 6d0f6bcf | 292 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
| 60e1dc15 | 293 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
| 6d0f6bcf | 294 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
| 60e1dc15 | 295 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
| 91e25769 PG |
296 | |
| 297 | /* | |
| 298 | * General PCI | |
| 299 | * Addresses are mapped 1-1. | |
| 300 | */ | |
| 6d0f6bcf JCPV |
301 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
| 302 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
| 303 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
| 304 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
| 305 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
| 306 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
| 60e1dc15 JH |
307 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
| 308 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
| 309 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 6d0f6bcf JCPV |
310 | |
| 311 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
| 312 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
| 313 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
| 314 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
| 315 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
| 316 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
| 60e1dc15 JH |
317 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
| 318 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
| 319 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
| 91e25769 PG |
320 | |
| 321 | #if defined(CONFIG_PCI) | |
| 322 | ||
| 323 | #define PCI_64BIT | |
| 324 | #define PCI_ONE_PCI1 | |
| 325 | #if defined(PCI_64BIT) | |
| 326 | #undef PCI_ALL_PCI1 | |
| 327 | #undef PCI_TWO_PCI1 | |
| 328 | #undef PCI_ONE_PCI1 | |
| 329 | #endif | |
| 330 | ||
| 91e25769 PG |
331 | #undef CONFIG_EEPRO100 |
| 332 | #undef CONFIG_TULIP | |
| 333 | ||
| 334 | #if !defined(CONFIG_PCI_PNP) | |
| 335 | #define PCI_ENET0_IOADDR 0xFIXME | |
| 336 | #define PCI_ENET0_MEMADDR 0xFIXME | |
| 337 | #define PCI_IDSEL_NUMBER 0xFIXME | |
| 338 | #endif | |
| 339 | ||
| 340 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 6d0f6bcf | 341 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| 91e25769 PG |
342 | |
| 343 | #endif /* CONFIG_PCI */ | |
| 344 | ||
| 345 | /* | |
| 346 | * TSEC configuration | |
| 347 | */ | |
| 348 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
| 349 | ||
| 350 | #if defined(CONFIG_TSEC_ENET) | |
| 91e25769 | 351 | |
| 255a3577 KP |
352 | #define CONFIG_TSEC1 1 |
| 353 | #define CONFIG_TSEC1_NAME "TSEC0" | |
| 354 | #define CONFIG_TSEC2 1 | |
| 355 | #define CONFIG_TSEC2_NAME "TSEC1" | |
| 91e25769 PG |
356 | #define CONFIG_PHY_BCM5421S 1 |
| 357 | #define TSEC1_PHY_ADDR 0x19 | |
| 358 | #define TSEC2_PHY_ADDR 0x1a | |
| 359 | #define TSEC1_PHYIDX 0 | |
| 360 | #define TSEC2_PHYIDX 0 | |
| 3a79013e AF |
361 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 362 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 91e25769 PG |
363 | |
| 364 | /* Options are: TSEC[0-1] */ | |
| 365 | #define CONFIG_ETHPRIME "TSEC0" | |
| 366 | ||
| 367 | #endif /* CONFIG_TSEC_ENET */ | |
| 368 | ||
| 369 | /* | |
| 370 | * Environment | |
| 371 | */ | |
| 6d0f6bcf | 372 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 373 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 374 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) |
| 0e8d1586 JCPV |
375 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 376 | #define CONFIG_ENV_SIZE 0x2000 | |
| 91e25769 PG |
377 | |
| 378 | /* Address and size of Redundant Environment Sector */ | |
| 0e8d1586 JCPV |
379 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
| 380 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 91e25769 PG |
381 | |
| 382 | #else | |
| 93f6d725 | 383 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 384 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 0e8d1586 | 385 | #define CONFIG_ENV_SIZE 0x2000 |
| 91e25769 PG |
386 | #endif |
| 387 | ||
| 388 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 389 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 91e25769 | 390 | |
| 079a136c JL |
391 | /* |
| 392 | * BOOTP options | |
| 393 | */ | |
| 394 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 395 | #define CONFIG_BOOTP_BOOTPATH | |
| 396 | #define CONFIG_BOOTP_GATEWAY | |
| 397 | #define CONFIG_BOOTP_HOSTNAME | |
| 398 | ||
| 866e3089 JL |
399 | /* |
| 400 | * Command line configuration. | |
| 401 | */ | |
| 866e3089 | 402 | |
| 91e25769 | 403 | #if defined(CONFIG_PCI) |
| e496865e | 404 | #define CONFIG_CMD_PCI |
| 91e25769 | 405 | #endif |
| 866e3089 | 406 | |
| 91e25769 PG |
407 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 408 | ||
| 409 | /* | |
| 410 | * Miscellaneous configurable options | |
| 411 | */ | |
| 6d0f6bcf JCPV |
412 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 413 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 91e25769 | 414 | |
| 866e3089 | 415 | #if defined(CONFIG_CMD_KGDB) |
| 60e1dc15 | 416 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 91e25769 | 417 | #else |
| 60e1dc15 | 418 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 91e25769 PG |
419 | #endif |
| 420 | ||
| 60e1dc15 JH |
421 | /* Print Buffer Size */ |
| 422 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
| 423 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 424 | /* Boot Argument Buffer Size */ | |
| 425 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 91e25769 PG |
426 | |
| 427 | /* | |
| 428 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 429 | * have to be in the first 256 MB of memory, since this is |
| 91e25769 PG |
430 | * the maximum mapped by the Linux kernel during initialization. |
| 431 | */ | |
| 60e1dc15 JH |
432 | /* Initial Memory map for Linux*/ |
| 433 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
| 91e25769 | 434 | |
| 6d0f6bcf | 435 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
| 91e25769 PG |
436 | |
| 437 | #if 1 /*528/264*/ | |
| 6d0f6bcf | 438 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
439 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 440 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 441 | HRCWL_CSB_TO_CLKIN |\ | |
| 442 | HRCWL_VCO_1X2 |\ | |
| 443 | HRCWL_CORE_TO_CSB_2X1) | |
| 444 | #elif 0 /*396/132*/ | |
| 6d0f6bcf | 445 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
446 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 447 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 448 | HRCWL_CSB_TO_CLKIN |\ | |
| 449 | HRCWL_VCO_1X4 |\ | |
| 450 | HRCWL_CORE_TO_CSB_3X1) | |
| 451 | #elif 0 /*264/132*/ | |
| 6d0f6bcf | 452 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
453 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 454 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 455 | HRCWL_CSB_TO_CLKIN |\ | |
| 456 | HRCWL_VCO_1X4 |\ | |
| 457 | HRCWL_CORE_TO_CSB_2X1) | |
| 458 | #elif 0 /*132/132*/ | |
| 6d0f6bcf | 459 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
460 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 461 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 462 | HRCWL_CSB_TO_CLKIN |\ | |
| 463 | HRCWL_VCO_1X4 |\ | |
| 464 | HRCWL_CORE_TO_CSB_1X1) | |
| 465 | #elif 0 /*264/264 */ | |
| 6d0f6bcf | 466 | #define CONFIG_SYS_HRCW_LOW (\ |
| 91e25769 PG |
467 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
| 468 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 469 | HRCWL_CSB_TO_CLKIN |\ | |
| 470 | HRCWL_VCO_1X4 |\ | |
| 471 | HRCWL_CORE_TO_CSB_1X1) | |
| 472 | #endif | |
| 473 | ||
| 474 | #if defined(PCI_64BIT) | |
| 6d0f6bcf | 475 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 91e25769 PG |
476 | HRCWH_PCI_HOST |\ |
| 477 | HRCWH_64_BIT_PCI |\ | |
| 478 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 479 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
| 480 | HRCWH_CORE_ENABLE |\ | |
| 481 | HRCWH_FROM_0X00000100 |\ | |
| 482 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 483 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 484 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 485 | HRCWH_TSEC1M_IN_GMII |\ | |
| 60e1dc15 | 486 | HRCWH_TSEC2M_IN_GMII) |
| 91e25769 | 487 | #else |
| 6d0f6bcf | 488 | #define CONFIG_SYS_HRCW_HIGH (\ |
| 91e25769 PG |
489 | HRCWH_PCI_HOST |\ |
| 490 | HRCWH_32_BIT_PCI |\ | |
| 491 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 492 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
| 493 | HRCWH_CORE_ENABLE |\ | |
| 494 | HRCWH_FROM_0X00000100 |\ | |
| 495 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 496 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 497 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 498 | HRCWH_TSEC1M_IN_GMII |\ | |
| 60e1dc15 | 499 | HRCWH_TSEC2M_IN_GMII) |
| 91e25769 PG |
500 | #endif |
| 501 | ||
| 502 | /* System IO Config */ | |
| 3c9b1ee1 | 503 | #define CONFIG_SYS_SICRH 0 |
| 6d0f6bcf | 504 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
| 91e25769 | 505 | |
| 6d0f6bcf | 506 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
| 60e1dc15 JH |
507 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
| 508 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
| 91e25769 | 509 | |
| 60e1dc15 | 510 | /* #define CONFIG_SYS_HID0_FINAL (\ |
| 91e25769 PG |
511 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
| 512 | HID0_ENABLE_M_BIT |\ | |
| 60e1dc15 | 513 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
| 91e25769 | 514 | |
| 6d0f6bcf | 515 | #define CONFIG_SYS_HID2 HID2_HBE |
| 91e25769 | 516 | |
| 31d82672 BB |
517 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
| 518 | ||
| 91e25769 | 519 | /* DDR @ 0x00000000 */ |
| 60e1dc15 | 520 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
| 72cd4087 | 521 | | BATL_PP_RW \ |
| 60e1dc15 JH |
522 | | BATL_MEMCOHERENCE) |
| 523 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
| 524 | | BATU_BL_256M \ | |
| 525 | | BATU_VS \ | |
| 526 | | BATU_VP) | |
| 91e25769 PG |
527 | |
| 528 | /* PCI @ 0x80000000 */ | |
| 529 | #ifdef CONFIG_PCI | |
| 842033e6 | 530 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 60e1dc15 | 531 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
| 72cd4087 | 532 | | BATL_PP_RW \ |
| 60e1dc15 JH |
533 | | BATL_MEMCOHERENCE) |
| 534 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
| 535 | | BATU_BL_256M \ | |
| 536 | | BATU_VS \ | |
| 537 | | BATU_VP) | |
| 538 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 72cd4087 | 539 | | BATL_PP_RW \ |
| 60e1dc15 JH |
540 | | BATL_CACHEINHIBIT \ |
| 541 | | BATL_GUARDEDSTORAGE) | |
| 542 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
| 543 | | BATU_BL_256M \ | |
| 544 | | BATU_VS \ | |
| 545 | | BATU_VP) | |
| 91e25769 | 546 | #else |
| 6d0f6bcf JCPV |
547 | #define CONFIG_SYS_IBAT1L (0) |
| 548 | #define CONFIG_SYS_IBAT1U (0) | |
| 549 | #define CONFIG_SYS_IBAT2L (0) | |
| 550 | #define CONFIG_SYS_IBAT2U (0) | |
| 91e25769 PG |
551 | #endif |
| 552 | ||
| 553 | #ifdef CONFIG_MPC83XX_PCI2 | |
| 60e1dc15 | 554 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
| 72cd4087 | 555 | | BATL_PP_RW \ |
| 60e1dc15 JH |
556 | | BATL_MEMCOHERENCE) |
| 557 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
| 558 | | BATU_BL_256M \ | |
| 559 | | BATU_VS \ | |
| 560 | | BATU_VP) | |
| 561 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 72cd4087 | 562 | | BATL_PP_RW \ |
| 60e1dc15 JH |
563 | | BATL_CACHEINHIBIT \ |
| 564 | | BATL_GUARDEDSTORAGE) | |
| 565 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
| 566 | | BATU_BL_256M \ | |
| 567 | | BATU_VS \ | |
| 568 | | BATU_VP) | |
| 91e25769 | 569 | #else |
| 6d0f6bcf JCPV |
570 | #define CONFIG_SYS_IBAT3L (0) |
| 571 | #define CONFIG_SYS_IBAT3U (0) | |
| 572 | #define CONFIG_SYS_IBAT4L (0) | |
| 573 | #define CONFIG_SYS_IBAT4U (0) | |
| 91e25769 PG |
574 | #endif |
| 575 | ||
| 576 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ | |
| 60e1dc15 | 577 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
| 72cd4087 | 578 | | BATL_PP_RW \ |
| 60e1dc15 JH |
579 | | BATL_CACHEINHIBIT \ |
| 580 | | BATL_GUARDEDSTORAGE) | |
| 581 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
| 582 | | BATU_BL_256M \ | |
| 583 | | BATU_VS \ | |
| 584 | | BATU_VP) | |
| 91e25769 | 585 | |
| 7d6a0982 JH |
586 | /* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
| 587 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE \ | |
| 72cd4087 | 588 | | BATL_PP_RW \ |
| 60e1dc15 JH |
589 | | BATL_MEMCOHERENCE \ |
| 590 | | BATL_GUARDEDSTORAGE) | |
| 7d6a0982 JH |
591 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE \ |
| 592 | | BATU_BL_256M \ | |
| 593 | | BATU_VS \ | |
| 594 | | BATU_VP) | |
| 6d0f6bcf JCPV |
595 | |
| 596 | #define CONFIG_SYS_IBAT7L (0) | |
| 597 | #define CONFIG_SYS_IBAT7U (0) | |
| 598 | ||
| 599 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
| 600 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
| 601 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
| 602 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
| 603 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
| 604 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
| 605 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
| 606 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
| 607 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
| 608 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
| 609 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
| 610 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
| 611 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
| 612 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
| 613 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
| 614 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
| 91e25769 | 615 | |
| 866e3089 | 616 | #if defined(CONFIG_CMD_KGDB) |
| 91e25769 | 617 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
| 91e25769 PG |
618 | #endif |
| 619 | ||
| 620 | /* | |
| 621 | * Environment Configuration | |
| 622 | */ | |
| 623 | #define CONFIG_ENV_OVERWRITE | |
| 624 | ||
| 625 | #if defined(CONFIG_TSEC_ENET) | |
| 10327dc5 | 626 | #define CONFIG_HAS_ETH0 |
| 91e25769 | 627 | #define CONFIG_HAS_ETH1 |
| 91e25769 PG |
628 | #endif |
| 629 | ||
| 91e25769 | 630 | #define CONFIG_HOSTNAME SBC8349 |
| 8b3637c6 | 631 | #define CONFIG_ROOTPATH "/tftpboot/rootfs" |
| b3f44c21 | 632 | #define CONFIG_BOOTFILE "uImage" |
| 91e25769 | 633 | |
| 60e1dc15 JH |
634 | /* default location for tftp and bootm */ |
| 635 | #define CONFIG_LOADADDR 800000 | |
| 91e25769 | 636 | |
| 60e1dc15 | 637 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 91e25769 PG |
638 | |
| 639 | #define CONFIG_BAUDRATE 115200 | |
| 640 | ||
| 641 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 642 | "netdev=eth0\0" \ | |
| a99715b8 | 643 | "hostname=sbc8349\0" \ |
| 91e25769 PG |
644 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 645 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 646 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 647 | "addip=setenv bootargs ${bootargs} " \ | |
| 648 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 649 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 650 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
| 651 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 652 | "bootm ${kernel_addr}\0" \ | |
| 653 | "flash_self=run ramargs addip addtty;" \ | |
| 654 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
| 655 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
| 656 | "bootm\0" \ | |
| 657 | "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ | |
| fe613cdd | 658 | "update=protect off ff800000 ff83ffff; " \ |
| 60e1dc15 | 659 | "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ |
| d8ab58b2 | 660 | "upd=run load update\0" \ |
| 79f516bc | 661 | "fdtaddr=780000\0" \ |
| a99715b8 | 662 | "fdtfile=sbc8349.dtb\0" \ |
| 91e25769 PG |
663 | "" |
| 664 | ||
| 60e1dc15 JH |
665 | #define CONFIG_NFSBOOTCOMMAND \ |
| 666 | "setenv bootargs root=/dev/nfs rw " \ | |
| 667 | "nfsroot=$serverip:$rootpath " \ | |
| 668 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
| 669 | "$netdev:off " \ | |
| 670 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 671 | "tftp $loadaddr $bootfile;" \ | |
| 672 | "tftp $fdtaddr $fdtfile;" \ | |
| 673 | "bootm $loadaddr - $fdtaddr" | |
| 91e25769 PG |
674 | |
| 675 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 60e1dc15 JH |
676 | "setenv bootargs root=/dev/ram rw " \ |
| 677 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 678 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 679 | "tftp $loadaddr $bootfile;" \ | |
| 680 | "tftp $fdtaddr $fdtfile;" \ | |
| 681 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 91e25769 PG |
682 | |
| 683 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 684 | ||
| 685 | #endif /* __CONFIG_H */ |