projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c646bba6 JH |
1 | /* |
| 2 | * Copyright 2007 Wind River Systems <www.windriver.com> | |
| 3 | * Copyright 2007 Embedded Specialties, Inc. | |
| 4 | * Joe Hamman <joe.hamman@embeddedspecialties.com> | |
| 5 | * | |
| 6 | * Copyright 2006 Freescale Semiconductor. | |
| 7 | * | |
| 8 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) | |
| 9 | * | |
| 3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
| c646bba6 JH |
11 | */ |
| 12 | ||
| 13 | /* | |
| 14 | * SBC8641D board configuration file | |
| 15 | * | |
| 16 | * Make sure you change the MAC address and other network params first, | |
| 92ac5208 | 17 | * search for CONFIG_SERVERIP, etc in this file. |
| c646bba6 JH |
18 | */ |
| 19 | ||
| 20 | #ifndef __CONFIG_H | |
| 21 | #define __CONFIG_H | |
| 22 | ||
| 6a48109d | 23 | |
| c646bba6 | 24 | /* High Level Configuration Options */ |
| c646bba6 JH |
25 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ |
| 26 | #define CONFIG_SBC8641D 1 /* SBC8641D board specific */ | |
| 7649a590 | 27 | #define CONFIG_MP 1 /* support multiple processors */ |
| c646bba6 JH |
28 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| 29 | ||
| 2ae18241 WD |
30 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
| 31 | ||
| c646bba6 | 32 | #ifdef RUN_DIAG |
| 6d0f6bcf | 33 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
| c646bba6 JH |
34 | #endif |
| 35 | ||
| 6d0f6bcf | 36 | #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 |
| c646bba6 | 37 | |
| 1266df88 BB |
38 | /* |
| 39 | * virtual address to be used for temporary mappings. There | |
| 40 | * should be 128k free at this VA. | |
| 41 | */ | |
| 42 | #define CONFIG_SYS_SCRATCH_VA 0xe8000000 | |
| 43 | ||
| 7cee1dfd KG |
44 | #define CONFIG_SYS_SRIO |
| 45 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
| 46 | ||
| cca34967 | 47 | #define CONFIG_PCI 1 /* Enable PCIE */ |
| 46f3e385 KG |
48 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ |
| 49 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| cca34967 | 50 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 842033e6 | 51 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
| 713d8186 | 52 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
| c646bba6 | 53 | |
| 53677ef1 | 54 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| c646bba6 JH |
55 | #define CONFIG_ENV_OVERWRITE |
| 56 | ||
| 4bbfd3e2 | 57 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
| 23f935c0 BB |
58 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| 59 | ||
| c646bba6 | 60 | #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ |
| 53677ef1 | 61 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| c646bba6 JH |
62 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 63 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 64 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
| 65 | #define CACHE_LINE_INTERLEAVING 0x20000000 | |
| 66 | #define PAGE_INTERLEAVING 0x21000000 | |
| 67 | #define BANK_INTERLEAVING 0x22000000 | |
| 68 | #define SUPER_BANK_INTERLEAVING 0x23000000 | |
| 69 | ||
| 70 | ||
| 71 | #define CONFIG_ALTIVEC 1 | |
| 72 | ||
| 73 | /* | |
| 74 | * L2CR setup -- make sure this is right for your board! | |
| 75 | */ | |
| 6d0f6bcf | 76 | #define CONFIG_SYS_L2 |
| c646bba6 JH |
77 | #define L2_INIT 0 |
| 78 | #define L2_ENABLE (L2CR_L2E) | |
| 79 | ||
| 80 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 81 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
| 82 | #endif | |
| 83 | ||
| 84 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 85 | ||
| 6d0f6bcf JCPV |
86 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
| 87 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
| 88 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| c646bba6 JH |
89 | |
| 90 | /* | |
| 91 | * Base addresses -- Note these are effective addresses where the | |
| 92 | * actual resources get mapped (not physical addresses) | |
| 93 | */ | |
| 6d0f6bcf JCPV |
94 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 95 | #define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ | |
| 96 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
| c646bba6 | 97 | |
| f698738e JL |
98 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
| 99 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
| ad19e7a5 | 100 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
| f698738e | 101 | |
| c646bba6 JH |
102 | /* |
| 103 | * DDR Setup | |
| 104 | */ | |
| 6d0f6bcf JCPV |
105 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
| 106 | #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ | |
| 107 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 108 | #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 | |
| 1266df88 | 109 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
| c646bba6 JH |
110 | #define CONFIG_VERY_BIG_RAM |
| 111 | ||
| 9bd4e591 KG |
112 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 113 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 114 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 115 | ||
| c646bba6 JH |
116 | #if defined(CONFIG_SPD_EEPROM) |
| 117 | /* | |
| 118 | * Determine DDR configuration from I2C interface. | |
| 119 | */ | |
| 120 | #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ | |
| 121 | #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ | |
| 122 | #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ | |
| 123 | #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ | |
| 124 | ||
| 125 | #else | |
| 126 | /* | |
| 127 | * Manually set up DDR1 & DDR2 parameters | |
| 128 | */ | |
| 129 | ||
| 6d0f6bcf JCPV |
130 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
| 131 | ||
| 132 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
| 133 | #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 | |
| 134 | #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 | |
| 135 | #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 | |
| 136 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 | |
| 137 | #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 | |
| 138 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 | |
| 139 | #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 | |
| 140 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 141 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 | |
| 142 | #define CONFIG_SYS_DDR_TIMING_1 0x38377322 | |
| 143 | #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 | |
| 144 | #define CONFIG_SYS_DDR_CFG_1A 0x43008008 | |
| 145 | #define CONFIG_SYS_DDR_CFG_2 0x24401000 | |
| 146 | #define CONFIG_SYS_DDR_MODE_1 0x23c00542 | |
| 147 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 148 | #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 | |
| 149 | #define CONFIG_SYS_DDR_INTERVAL 0x05080100 | |
| 150 | #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 | |
| 151 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 152 | #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 | |
| 153 | ||
| 154 | #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F | |
| 155 | #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 | |
| 156 | #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 | |
| 157 | #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 | |
| 158 | #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 | |
| 159 | #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 | |
| 160 | #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 | |
| 161 | #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 | |
| 162 | #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 | |
| 163 | #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 | |
| 164 | #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 | |
| 165 | #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 | |
| 166 | #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 | |
| 167 | #define CONFIG_SYS_DDR2_CFG_2 0x24401000 | |
| 168 | #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 | |
| 169 | #define CONFIG_SYS_DDR2_MODE_2 0x00000000 | |
| 170 | #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 | |
| 171 | #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 | |
| 172 | #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 | |
| 173 | #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 | |
| 174 | #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 | |
| c646bba6 JH |
175 | |
| 176 | ||
| 177 | #endif | |
| 178 | ||
| 32628c50 | 179 | /* #define CONFIG_ID_EEPROM 1 |
| c646bba6 JH |
180 | #define ID_EEPROM_ADDR 0x57 */ |
| 181 | ||
| 182 | /* | |
| 183 | * The SBC8641D contains 16MB flash space at ff000000. | |
| 184 | */ | |
| 6d0f6bcf | 185 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
| c646bba6 JH |
186 | |
| 187 | /* Flash */ | |
| 6d0f6bcf JCPV |
188 | #define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ |
| 189 | #define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ | |
| c646bba6 JH |
190 | |
| 191 | /* 64KB EEPROM */ | |
| 6d0f6bcf JCPV |
192 | #define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ |
| 193 | #define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ | |
| c646bba6 JH |
194 | |
| 195 | /* EPLD - User switches, board id, LEDs */ | |
| 6d0f6bcf JCPV |
196 | #define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ |
| 197 | #define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ | |
| c646bba6 JH |
198 | |
| 199 | /* Local bus SDRAM 128MB */ | |
| 6d0f6bcf JCPV |
200 | #define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ |
| 201 | #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ | |
| 202 | #define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ | |
| 203 | #define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 JH |
204 | |
| 205 | /* Disk on Chip (DOC) 128MB */ | |
| 6d0f6bcf JCPV |
206 | #define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ |
| 207 | #define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 JH |
208 | |
| 209 | /* LCD */ | |
| 6d0f6bcf JCPV |
210 | #define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ |
| 211 | #define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 JH |
212 | |
| 213 | /* Control logic & misc peripherals */ | |
| 6d0f6bcf JCPV |
214 | #define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ |
| 215 | #define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ | |
| c646bba6 | 216 | |
| 6d0f6bcf JCPV |
217 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 218 | #define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ | |
| c646bba6 | 219 | |
| 6d0f6bcf JCPV |
220 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 221 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 222 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 14d0a02a | 223 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| bf9a8c34 | 224 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
| c646bba6 | 225 | |
| 00b1883a | 226 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
227 | #define CONFIG_SYS_FLASH_CFI |
| 228 | #define CONFIG_SYS_WRITE_SWAPPED_DATA | |
| 229 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 230 | #define CONFIG_SYS_FLASH_PROTECTION | |
| c646bba6 JH |
231 | |
| 232 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 233 | ||
| 6d0f6bcf JCPV |
234 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 235 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
| 236 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| c646bba6 | 237 | #else |
| 6d0f6bcf | 238 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
| c646bba6 | 239 | #endif |
| 553f0982 | 240 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| c646bba6 | 241 | |
| 25ddd1fb | 242 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 243 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| c646bba6 | 244 | |
| ecdc3df6 | 245 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
| 7229c3c7 | 246 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ |
| c646bba6 JH |
247 | |
| 248 | /* Serial Port */ | |
| 249 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
250 | #define CONFIG_SYS_NS16550_SERIAL |
| 251 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 252 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| c646bba6 | 253 | |
| 6d0f6bcf | 254 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| c646bba6 JH |
255 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 256 | ||
| 6d0f6bcf JCPV |
257 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 258 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| c646bba6 | 259 | |
| c646bba6 JH |
260 | /* |
| 261 | * I2C | |
| 262 | */ | |
| 00f792e0 HS |
263 | #define CONFIG_SYS_I2C |
| 264 | #define CONFIG_SYS_I2C_FSL | |
| 265 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
| 266 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 267 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 | |
| 268 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
| c646bba6 JH |
269 | |
| 270 | /* | |
| 271 | * RapidIO MMU | |
| 272 | */ | |
| 7cee1dfd KG |
273 | #define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ |
| 274 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE | |
| 275 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ | |
| c646bba6 JH |
276 | |
| 277 | /* | |
| 278 | * General PCI | |
| 279 | * Addresses are mapped 1-1. | |
| 280 | */ | |
| 46f3e385 KG |
281 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 |
| 282 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
| 283 | #define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS | |
| 284 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
| 285 | #define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 | |
| 286 | #define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS | |
| 287 | #define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS | |
| 288 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ | |
| 289 | ||
| 290 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
| 291 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
| 292 | #define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS | |
| 293 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ | |
| 294 | #define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 | |
| 295 | #define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS | |
| 296 | #define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS | |
| 297 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ | |
| c646bba6 JH |
298 | |
| 299 | #if defined(CONFIG_PCI) | |
| 300 | ||
| 301 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 302 | ||
| 6d0f6bcf | 303 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
| c646bba6 | 304 | |
| 53677ef1 | 305 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| c646bba6 JH |
306 | |
| 307 | #undef CONFIG_EEPRO100 | |
| 308 | #undef CONFIG_TULIP | |
| 309 | ||
| 310 | #if !defined(CONFIG_PCI_PNP) | |
| 311 | #define PCI_ENET0_IOADDR 0xe0000000 | |
| 312 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
| 53677ef1 | 313 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| c646bba6 JH |
314 | #endif |
| 315 | ||
| 316 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 317 | ||
| 318 | #define CONFIG_DOS_PARTITION | |
| 319 | #undef CONFIG_SCSI_AHCI | |
| 320 | ||
| 321 | #ifdef CONFIG_SCSI_AHCI | |
| 322 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
323 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 324 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 325 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 326 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| c646bba6 JH |
327 | #endif |
| 328 | ||
| 329 | #endif /* CONFIG_PCI */ | |
| 330 | ||
| 331 | #if defined(CONFIG_TSEC_ENET) | |
| 332 | ||
| c646bba6 JH |
333 | /* #define CONFIG_MII 1 */ /* MII PHY management */ |
| 334 | ||
| 335 | #define CONFIG_TSEC1 1 | |
| 336 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 337 | #define CONFIG_TSEC2 1 | |
| 338 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 339 | #define CONFIG_TSEC3 1 | |
| 340 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 341 | #define CONFIG_TSEC4 1 | |
| 342 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| 343 | ||
| 344 | #define TSEC1_PHY_ADDR 0x1F | |
| 345 | #define TSEC2_PHY_ADDR 0x00 | |
| 346 | #define TSEC3_PHY_ADDR 0x01 | |
| 347 | #define TSEC4_PHY_ADDR 0x02 | |
| 348 | #define TSEC1_PHYIDX 0 | |
| 349 | #define TSEC2_PHYIDX 0 | |
| 350 | #define TSEC3_PHYIDX 0 | |
| 351 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
352 | #define TSEC1_FLAGS TSEC_GIGABIT |
| 353 | #define TSEC2_FLAGS TSEC_GIGABIT | |
| 354 | #define TSEC3_FLAGS TSEC_GIGABIT | |
| 355 | #define TSEC4_FLAGS TSEC_GIGABIT | |
| c646bba6 | 356 | |
| 6d0f6bcf | 357 | #define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ |
| c646bba6 JH |
358 | |
| 359 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 360 | ||
| 361 | #endif /* CONFIG_TSEC_ENET */ | |
| 362 | ||
| 363 | /* | |
| 364 | * BAT0 2G Cacheable, non-guarded | |
| 365 | * 0x0000_0000 2G DDR | |
| 366 | */ | |
| 6d0f6bcf JCPV |
367 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 368 | #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) | |
| 369 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) | |
| 370 | #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U | |
| c646bba6 JH |
371 | |
| 372 | /* | |
| 373 | * BAT1 1G Cache-inhibited, guarded | |
| 374 | * 0x8000_0000 512M PCI-Express 1 Memory | |
| 375 | * 0xa000_0000 512M PCI-Express 2 Memory | |
| 376 | * Changed it for operating from 0xd0000000 | |
| 377 | */ | |
| 46f3e385 | 378 | #define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ |
| c646bba6 | 379 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 46f3e385 KG |
380 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) |
| 381 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 382 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
| c646bba6 JH |
383 | |
| 384 | /* | |
| 385 | * BAT2 512M Cache-inhibited, guarded | |
| 386 | * 0xc000_0000 512M RapidIO Memory | |
| 387 | */ | |
| 7cee1dfd | 388 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ |
| c646bba6 | 389 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 7cee1dfd KG |
390 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) |
| 391 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 392 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| c646bba6 JH |
393 | |
| 394 | /* | |
| 395 | * BAT3 4M Cache-inhibited, guarded | |
| 396 | * 0xf800_0000 4M CCSR | |
| 397 | */ | |
| 6d0f6bcf | 398 | #define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ |
| c646bba6 | 399 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
400 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) |
| 401 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 402 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U | |
| c646bba6 | 403 | |
| f698738e JL |
404 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 405 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 406 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 407 | | BATL_GUARDEDSTORAGE) | |
| 408 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 409 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 410 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 411 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 412 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 413 | #endif | |
| 414 | ||
| c646bba6 JH |
415 | /* |
| 416 | * BAT4 32M Cache-inhibited, guarded | |
| 417 | * 0xe200_0000 16M PCI-Express 1 I/O | |
| 418 | * 0xe300_0000 16M PCI-Express 2 I/0 | |
| 419 | * Note that this is at 0xe0000000 | |
| 420 | */ | |
| 46f3e385 | 421 | #define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ |
| c646bba6 | 422 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 46f3e385 KG |
423 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) |
| 424 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 425 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
| c646bba6 JH |
426 | |
| 427 | /* | |
| 428 | * BAT5 128K Cacheable, non-guarded | |
| 429 | * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
| 430 | */ | |
| 6d0f6bcf JCPV |
431 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 432 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 433 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 434 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| c646bba6 JH |
435 | |
| 436 | /* | |
| 437 | * BAT6 32M Cache-inhibited, guarded | |
| 438 | * 0xfe00_0000 32M FLASH | |
| 439 | */ | |
| 6d0f6bcf | 440 | #define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ |
| c646bba6 | 441 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
442 | #define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) |
| 443 | #define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 444 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U | |
| c646bba6 | 445 | |
| bf9a8c34 BB |
446 | /* Map the last 1M of flash where we're running from reset */ |
| 447 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 448 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 14d0a02a | 449 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
| bf9a8c34 BB |
450 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 451 | | BATL_MEMCOHERENCE) | |
| 452 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 453 | ||
| 6d0f6bcf JCPV |
454 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 455 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
| 456 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
| 457 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
| c646bba6 JH |
458 | |
| 459 | /* | |
| 460 | * Environment | |
| 461 | */ | |
| 5a1aceb0 | 462 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| ecdc3df6 | 463 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
| 71d55116 | 464 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ |
| 0e8d1586 | 465 | #define CONFIG_ENV_SIZE 0x2000 |
| c646bba6 JH |
466 | |
| 467 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 468 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| c646bba6 | 469 | |
| ef0f2f57 JH |
470 | #define CONFIG_CMD_PING |
| 471 | #define CONFIG_CMD_I2C | |
| 472 | #define CONFIG_CMD_REGINFO | |
| c646bba6 JH |
473 | |
| 474 | #if defined(CONFIG_PCI) | |
| 475 | #define CONFIG_CMD_PCI | |
| 476 | #endif | |
| 477 | ||
| 478 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 479 | ||
| 480 | /* | |
| 481 | * Miscellaneous configurable options | |
| 482 | */ | |
| 6d0f6bcf JCPV |
483 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 484 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 73f75507 | 485 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| c646bba6 | 486 | |
| 30b52df9 | 487 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 488 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| c646bba6 | 489 | #else |
| 6d0f6bcf | 490 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| c646bba6 JH |
491 | #endif |
| 492 | ||
| 6d0f6bcf JCPV |
493 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 494 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 495 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| c646bba6 JH |
496 | |
| 497 | /* | |
| 498 | * For booting Linux, the board info and command line data | |
| 499 | * have to be in the first 8 MB of memory, since this is | |
| 500 | * the maximum mapped by the Linux kernel during initialization. | |
| 501 | */ | |
| 6d0f6bcf | 502 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| c646bba6 JH |
503 | |
| 504 | /* Cache Configuration */ | |
| 6d0f6bcf JCPV |
505 | #define CONFIG_SYS_DCACHE_SIZE 32768 |
| 506 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| 30b52df9 | 507 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 508 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| c646bba6 JH |
509 | #endif |
| 510 | ||
| 30b52df9 | 511 | #if defined(CONFIG_CMD_KGDB) |
| c646bba6 | 512 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| c646bba6 JH |
513 | #endif |
| 514 | ||
| 515 | /* | |
| 516 | * Environment Configuration | |
| 517 | */ | |
| 518 | ||
| 10327dc5 | 519 | #define CONFIG_HAS_ETH0 1 |
| c646bba6 JH |
520 | #define CONFIG_HAS_ETH1 1 |
| 521 | #define CONFIG_HAS_ETH2 1 | |
| 522 | #define CONFIG_HAS_ETH3 1 | |
| 523 | ||
| 524 | #define CONFIG_IPADDR 192.168.0.50 | |
| 525 | ||
| 526 | #define CONFIG_HOSTNAME sbc8641d | |
| 8b3637c6 | 527 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" |
| b3f44c21 | 528 | #define CONFIG_BOOTFILE "uImage" |
| c646bba6 JH |
529 | |
| 530 | #define CONFIG_SERVERIP 192.168.0.2 | |
| 531 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 532 | #define CONFIG_NETMASK 255.255.255.0 | |
| 533 | ||
| 534 | /* default location for tftp and bootm */ | |
| 535 | #define CONFIG_LOADADDR 1000000 | |
| 536 | ||
| 537 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 538 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 539 | ||
| 540 | #define CONFIG_BAUDRATE 115200 | |
| 541 | ||
| 542 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 543 | "netdev=eth0\0" \ | |
| 544 | "consoledev=ttyS0\0" \ | |
| 545 | "ramdiskaddr=2000000\0" \ | |
| 546 | "ramdiskfile=uRamdisk\0" \ | |
| 547 | "dtbaddr=400000\0" \ | |
| 548 | "dtbfile=sbc8641d.dtb\0" \ | |
| 549 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
| 550 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
| 551 | "maxcpus=1" | |
| 552 | ||
| 553 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 554 | "setenv bootargs root=/dev/nfs rw " \ | |
| 555 | "nfsroot=$serverip:$rootpath " \ | |
| 556 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 557 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 558 | "tftp $loadaddr $bootfile;" \ | |
| 559 | "tftp $dtbaddr $dtbfile;" \ | |
| 560 | "bootm $loadaddr - $dtbaddr" | |
| 561 | ||
| 562 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 563 | "setenv bootargs root=/dev/ram rw " \ | |
| 564 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 565 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 566 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 567 | "tftp $loadaddr $bootfile;" \ | |
| 568 | "tftp $dtbaddr $dtbfile;" \ | |
| 569 | "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
| 570 | ||
| 571 | #define CONFIG_FLASHBOOTCOMMAND \ | |
| 572 | "setenv bootargs root=/dev/ram rw " \ | |
| 573 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 574 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 575 | "bootm ffd00000 ffb00000 ffa00000" | |
| 576 | ||
| 577 | #define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND | |
| 578 | ||
| 579 | #endif /* __CONFIG_H */ |