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ca43ba18 HS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Heiko Schocher, DENX Software Engineering, <hs@denx.de>. | |
4 | * | |
5 | * From: | |
6 | * (C) Copyright 2003 | |
7 | * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | #undef USE_VGA_GRAPHICS | |
32 | ||
33 | /* Memory Map | |
6d3e0107 WD |
34 | * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB) |
35 | * 0x74000000 .... 0x740FFFFF -> CS#6 | |
36 | * 0x74100000 .... 0x741FFFFF -> CS#7 | |
37 | * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB | |
38 | * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE | |
39 | * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB) | |
40 | * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB) | |
41 | * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB) | |
42 | * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB) | |
43 | * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored) | |
44 | * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB) | |
45 | * | |
46 | * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1) | |
47 | * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF) | |
48 | * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF) | |
49 | * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF) | |
50 | * 0xEED00000 .... 0xEED00003 -> PCI-Bus | |
51 | * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers | |
52 | * 0xEF40003F .... 0xEF5FFFFF -> reserved | |
53 | * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB) | |
54 | * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB) | |
55 | * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices | |
56 | * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB) | |
57 | * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices | |
58 | * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) | |
59 | */ | |
ca43ba18 | 60 | |
9045f33c | 61 | #define CONFIG_SC3 1 |
ca43ba18 HS |
62 | #define CONFIG_4xx 1 |
63 | #define CONFIG_405GP 1 | |
64 | ||
65 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
3a8f28d0 | 66 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ |
ca43ba18 HS |
67 | |
68 | /* | |
6d3e0107 WD |
69 | * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range |
70 | * If undefined, IDE access uses a seperat emulation with higher access speed. | |
ca43ba18 | 71 | * Consider to inform your Linux IDE driver about the different addresses! |
639221c7 | 72 | * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE! |
ca43ba18 HS |
73 | */ |
74 | #define IDE_USES_ISA_EMULATION | |
75 | ||
76 | /*----------------------------------------------------------------------- | |
77 | * Serial Port | |
78 | *----------------------------------------------------------------------*/ | |
79 | #define CONFIG_SERIAL_MULTI | |
80 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
81 | /* | |
82 | * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input | |
83 | * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature | |
84 | */ | |
85 | #if CONFIG_SERIAL_SOFTWARE_FIFO | |
86 | #define CONFIG_POWER_DOWN | |
87 | #endif | |
88 | ||
89 | /* | |
90 | * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz | |
91 | */ | |
92 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
93 | ||
94 | /* | |
95 | * define CONFIG_BAUDRATE to the baudrate value you want to use as default | |
96 | */ | |
97 | #define CONFIG_BAUDRATE 115200 | |
f11033e7 | 98 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
ca43ba18 | 99 | |
1bbbbdd2 | 100 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 101 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
1bbbbdd2 WD |
102 | "echo" |
103 | ||
104 | #undef CONFIG_BOOTARGS | |
105 | ||
106 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
107 | "netdev=eth0\0" \ | |
108 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
109 | "nfsroot=${serverip}:${rootpath}\0" \ | |
110 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
cb482072 HS |
111 | "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \ |
112 | "rootfstype=jffs2\0" \ | |
1bbbbdd2 WD |
113 | "addip=setenv bootargs ${bootargs} " \ |
114 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
115 | ":${hostname}:${netdev}:off panic=1\0" \ | |
a7090b99 WD |
116 | "addcons=setenv bootargs ${bootargs} " \ |
117 | "console=ttyS0,${baudrate}\0" \ | |
118 | "flash_nfs=run nfsargs addip addcons;" \ | |
1bbbbdd2 | 119 | "bootm ${kernel_addr}\0" \ |
a7090b99 WD |
120 | "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \ |
121 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ | |
122 | "bootm\0" \ | |
1bbbbdd2 WD |
123 | "rootpath=/opt/eldk/ppc_4xx\0" \ |
124 | "bootfile=/tftpboot/sc3/uImage\0" \ | |
d0b6e140 | 125 | "u-boot=/tftpboot/sc3/u-boot.bin\0" \ |
74de7aef | 126 | "setup=tftp 200000 /tftpboot/sc3/setup.img;source 200000\0" \ |
1bbbbdd2 WD |
127 | "kernel_addr=FFE08000\0" \ |
128 | "" | |
129 | #undef CONFIG_BOOTCOMMAND | |
130 | ||
ca43ba18 | 131 | #define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ |
6d0f6bcf | 132 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
ca43ba18 HS |
133 | |
134 | #if 1 /* feel free to disable for development */ | |
135 | #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ | |
c37207d7 WD |
136 | #define CONFIG_AUTOBOOT_PROMPT \ |
137 | "\nSC3 - booting... stop with ENTER\n" | |
9045f33c WD |
138 | #define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */ |
139 | #define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */ | |
ca43ba18 HS |
140 | #endif |
141 | ||
142 | /* | |
143 | * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after | |
144 | * the CONFIG_BOOTDELAY delay to boot your machine | |
145 | */ | |
146 | #define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm" | |
147 | ||
148 | /* | |
149 | * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't | |
150 | * set different values at the u-boot prompt | |
151 | */ | |
152 | #ifdef USE_VGA_GRAPHICS | |
153 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re" | |
154 | #else | |
155 | #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp" | |
156 | #endif | |
157 | /* | |
158 | * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT | |
159 | * This reserves memory bank #4 for this purpose | |
160 | */ | |
161 | #undef CONFIG_ISP1161_PRESENT | |
162 | ||
163 | #undef CONFIG_LOADS_ECHO /* no echo on for serial download */ | |
6d0f6bcf | 164 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
ca43ba18 HS |
165 | |
166 | #define CONFIG_NET_MULTI | |
167 | /* #define CONFIG_EEPRO100_SROM_WRITE */ | |
168 | /* #define CONFIG_SHOW_MAC */ | |
169 | #define CONFIG_EEPRO100 | |
96e21f86 BW |
170 | |
171 | #define CONFIG_PPC4xx_EMAC | |
ca43ba18 HS |
172 | #define CONFIG_MII 1 /* add 405GP MII PHY management */ |
173 | #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ | |
174 | ||
079a136c JL |
175 | /* |
176 | * BOOTP options | |
177 | */ | |
178 | #define CONFIG_BOOTP_BOOTFILESIZE | |
179 | #define CONFIG_BOOTP_BOOTPATH | |
180 | #define CONFIG_BOOTP_GATEWAY | |
181 | #define CONFIG_BOOTP_HOSTNAME | |
182 | ||
183 | ||
46da1e96 JL |
184 | /* |
185 | * Command line configuration. | |
186 | */ | |
187 | #include <config_cmd_default.h> | |
188 | ||
189 | ||
74de7aef | 190 | #define CONFIG_CMD_CACHE |
46da1e96 JL |
191 | #define CONFIG_CMD_DATE |
192 | #define CONFIG_CMD_DHCP | |
46da1e96 | 193 | #define CONFIG_CMD_ELF |
74de7aef WD |
194 | #define CONFIG_CMD_I2C |
195 | #define CONFIG_CMD_IDE | |
196 | #define CONFIG_CMD_IRQ | |
197 | #define CONFIG_CMD_JFFS2 | |
198 | #define CONFIG_CMD_MII | |
199 | #define CONFIG_CMD_NAND | |
200 | #define CONFIG_CMD_NET | |
201 | #define CONFIG_CMD_PCI | |
202 | #define CONFIG_CMD_PING | |
203 | #define CONFIG_CMD_SOURCE | |
46da1e96 | 204 | |
ca43ba18 HS |
205 | |
206 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
207 | ||
208 | /* | |
209 | * Miscellaneous configurable options | |
210 | */ | |
6d0f6bcf JCPV |
211 | #define CONFIG_SYS_LONGHELP 1 /* undef to save memory */ |
212 | #define CONFIG_SYS_PROMPT "SC3> " /* Monitor Command Prompt */ | |
213 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
ca43ba18 | 214 | |
6d0f6bcf | 215 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
ca43ba18 | 216 | |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
218 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
ca43ba18 | 219 | |
6d0f6bcf JCPV |
220 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
221 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
ca43ba18 HS |
222 | |
223 | /* | |
6d0f6bcf JCPV |
224 | * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. |
225 | * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. | |
226 | * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. | |
ca43ba18 HS |
227 | * The Linux BASE_BAUD define should match this configuration. |
228 | * baseBaud = cpuClock/(uartDivisor*16) | |
6d0f6bcf | 229 | * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, |
ca43ba18 HS |
230 | * set Linux BASE_BAUD to 403200. |
231 | * | |
232 | * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to | |
233 | * (see 405GP datasheet for descritpion) | |
234 | */ | |
6d0f6bcf JCPV |
235 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ |
236 | #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ | |
237 | #define CONFIG_SYS_BASE_BAUD 921600 /* internal clock */ | |
ca43ba18 HS |
238 | |
239 | /* The following table includes the supported baudrates */ | |
6d0f6bcf | 240 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
ca43ba18 HS |
241 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} |
242 | ||
6d0f6bcf JCPV |
243 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ |
244 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ | |
ca43ba18 | 245 | |
6d0f6bcf | 246 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
ca43ba18 HS |
247 | |
248 | /*----------------------------------------------------------------------- | |
249 | * IIC stuff | |
250 | *----------------------------------------------------------------------- | |
251 | */ | |
252 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
f11033e7 | 253 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
d0b0dcaa | 254 | #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ |
ca43ba18 HS |
255 | |
256 | #define I2C_INIT | |
257 | #define I2C_ACTIVE 0 | |
258 | #define I2C_TRISTATE 0 | |
259 | ||
6d0f6bcf JCPV |
260 | #define CONFIG_SYS_I2C_SPEED 100000 /* use the standard 100kHz speed */ |
261 | #define CONFIG_SYS_I2C_SLAVE 0x7F /* mask valid bits */ | |
ca43ba18 HS |
262 | |
263 | #define CONFIG_RTC_DS1337 | |
6d0f6bcf | 264 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
ca43ba18 HS |
265 | |
266 | /*----------------------------------------------------------------------- | |
267 | * PCI stuff | |
268 | *----------------------------------------------------------------------- | |
269 | */ | |
f11033e7 WD |
270 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
271 | #define PCI_HOST_FORCE 1 /* configure as pci host */ | |
272 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ | |
ca43ba18 | 273 | |
f11033e7 WD |
274 | #define CONFIG_PCI /* include pci support */ |
275 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ | |
276 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
277 | /* resource configuration */ | |
ca43ba18 HS |
278 | |
279 | /* If you want to see, whats connected to your PCI bus */ | |
280 | /* #define CONFIG_PCI_SCAN_SHOW */ | |
281 | ||
6d0f6bcf JCPV |
282 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ |
283 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ | |
284 | #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ | |
285 | #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ | |
286 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ | |
287 | #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ | |
288 | #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ | |
289 | #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ | |
ca43ba18 HS |
290 | |
291 | /*----------------------------------------------------------------------- | |
292 | * External peripheral base address | |
293 | *----------------------------------------------------------------------- | |
294 | */ | |
46da1e96 | 295 | #if !defined(CONFIG_CMD_IDE) |
ca43ba18 | 296 | |
f11033e7 WD |
297 | #undef CONFIG_IDE_LED /* no led for ide supported */ |
298 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
ca43ba18 HS |
299 | |
300 | /*----------------------------------------------------------------------- | |
301 | * IDE/ATA stuff | |
302 | *----------------------------------------------------------------------- | |
303 | */ | |
46da1e96 | 304 | #else |
ca43ba18 HS |
305 | #define CONFIG_START_IDE 1 /* check, if use IDE */ |
306 | ||
f11033e7 WD |
307 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
308 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
309 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
ca43ba18 HS |
310 | |
311 | #define CONFIG_ATAPI | |
312 | #define CONFIG_DOS_PARTITION | |
6d0f6bcf | 313 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ |
ca43ba18 HS |
314 | |
315 | #ifndef IDE_USES_ISA_EMULATION | |
316 | ||
317 | /* New and faster access */ | |
6d0f6bcf | 318 | #define CONFIG_SYS_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */ |
ca43ba18 HS |
319 | |
320 | /* How many IDE busses are available */ | |
6d0f6bcf | 321 | #define CONFIG_SYS_IDE_MAXBUS 1 |
ca43ba18 HS |
322 | |
323 | /* What IDE ports are available */ | |
6d0f6bcf JCPV |
324 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x000 /* first is available */ |
325 | #undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ | |
ca43ba18 HS |
326 | |
327 | /* access to the data port is calculated: | |
6d0f6bcf JCPV |
328 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ |
329 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
ca43ba18 HS |
330 | |
331 | /* access to the registers is calculated: | |
6d0f6bcf JCPV |
332 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ |
333 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
ca43ba18 HS |
334 | |
335 | /* access to the alternate register is calculated: | |
6d0f6bcf JCPV |
336 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ |
337 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */ | |
ca43ba18 HS |
338 | |
339 | #else /* IDE_USES_ISA_EMULATION */ | |
340 | ||
6d0f6bcf | 341 | #define CONFIG_SYS_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */ |
ca43ba18 HS |
342 | |
343 | /* How many IDE busses are available */ | |
6d0f6bcf | 344 | #define CONFIG_SYS_IDE_MAXBUS 1 |
ca43ba18 HS |
345 | |
346 | /* What IDE ports are available */ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* first is available */ |
348 | #undef CONFIG_SYS_ATA_IDE1_OFFSET /* second not available */ | |
ca43ba18 HS |
349 | |
350 | /* access to the data port is calculated: | |
6d0f6bcf JCPV |
351 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_DATA_OFFSET + 0 */ |
352 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ | |
ca43ba18 HS |
353 | |
354 | /* access to the registers is calculated: | |
6d0f6bcf JCPV |
355 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_REG_OFFSET + [1..7] */ |
356 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ | |
ca43ba18 HS |
357 | |
358 | /* access to the alternate register is calculated: | |
6d0f6bcf JCPV |
359 | CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_IDE0_OFFSET + CONFIG_SYS_ATA_ALT_OFFSET + 6 */ |
360 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */ | |
ca43ba18 HS |
361 | |
362 | #endif /* IDE_USES_ISA_EMULATION */ | |
363 | ||
46da1e96 | 364 | #endif |
ca43ba18 HS |
365 | |
366 | /* | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 |
368 | #define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 | |
369 | #define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 | |
ca43ba18 HS |
370 | */ |
371 | ||
372 | /*----------------------------------------------------------------------- | |
373 | * Start addresses for the final memory configuration | |
374 | * (Set up by the startup code) | |
6d0f6bcf | 375 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
ca43ba18 | 376 | * |
6d0f6bcf JCPV |
377 | * CONFIG_SYS_FLASH_BASE -> start address of internal flash |
378 | * CONFIG_SYS_MONITOR_BASE -> start of u-boot | |
ca43ba18 | 379 | */ |
6d0f6bcf JCPV |
380 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
381 | #define CONFIG_SYS_FLASH_BASE 0xFFE00000 | |
382 | #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ | |
383 | #define CONFIG_SYS_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */ | |
384 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ | |
ca43ba18 HS |
385 | |
386 | /* | |
387 | * For booting Linux, the board info and command line data | |
388 | * have to be in the first 8 MiB of memory, since this is | |
389 | * the maximum mapped by the Linux kernel during initialization. | |
390 | */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
ca43ba18 | 392 | /*----------------------------------------------------------------------- |
f11033e7 | 393 | * FLASH organization ## FIXME: lookup in datasheet |
ca43ba18 | 394 | */ |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
396 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
ca43ba18 | 397 | |
6d0f6bcf | 398 | #define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */ |
00b1883a | 399 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ |
6d0f6bcf JCPV |
400 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */ |
401 | #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ | |
402 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
403 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
404 | #define CONFIG_SYS_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */ | |
ca43ba18 | 405 | |
5a1aceb0 JCPV |
406 | #define CONFIG_ENV_IS_IN_FLASH 1 |
407 | #ifdef CONFIG_ENV_IS_IN_FLASH | |
0e8d1586 JCPV |
408 | #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ |
409 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
410 | #define CONFIG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ | |
6d3e0107 WD |
411 | |
412 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
413 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
414 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
6d3e0107 | 415 | |
ca43ba18 HS |
416 | #endif |
417 | /* let us changing anything in our environment */ | |
418 | #define CONFIG_ENV_OVERWRITE | |
419 | ||
420 | /* | |
421 | * NAND-FLASH stuff | |
422 | */ | |
6d0f6bcf | 423 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
6d0f6bcf | 424 | #define CONFIG_SYS_NAND_BASE 0x77D00000 |
ca43ba18 | 425 | |
cb482072 HS |
426 | #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ |
427 | ||
51056dd9 | 428 | /* No command line, one static partition */ |
68d7d651 | 429 | #undef CONFIG_CMD_MTDPARTS |
cb482072 | 430 | #define CONFIG_JFFS2_DEV "nand0" |
51056dd9 WD |
431 | #define CONFIG_JFFS2_PART_SIZE 0x01000000 |
432 | #define CONFIG_JFFS2_PART_OFFSET 0x00000000 | |
cb482072 | 433 | |
ca43ba18 HS |
434 | /* |
435 | * Init Memory Controller: | |
436 | * | |
437 | */ | |
438 | ||
6d0f6bcf | 439 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE |
ca43ba18 HS |
440 | #define FLASH_BASE1_PRELIM 0 |
441 | ||
442 | /*----------------------------------------------------------------------- | |
443 | * Some informations about the internal SRAM (OCM=On Chip Memory) | |
444 | * | |
6d0f6bcf JCPV |
445 | * CONFIG_SYS_OCM_DATA_ADDR -> location |
446 | * CONFIG_SYS_OCM_DATA_SIZE -> size | |
ca43ba18 HS |
447 | */ |
448 | ||
6d0f6bcf JCPV |
449 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
450 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 | |
451 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 | |
ca43ba18 HS |
452 | |
453 | /*----------------------------------------------------------------------- | |
454 | * Definitions for initial stack pointer and data area (in DPRAM): | |
455 | * - we are using the internal 4k SRAM, so we don't need data cache mapping | |
6d0f6bcf | 456 | * - internal SRAM (OCM=On Chip Memory) is placed to CONFIG_SYS_OCM_DATA_ADDR |
ca43ba18 | 457 | * - Stackpointer will be located to |
6d0f6bcf | 458 | * (CONFIG_SYS_INIT_RAM_ADDR&0xFFFF0000) | (CONFIG_SYS_INIT_SP_OFFSET&0x0000FFFF) |
a47a12be | 459 | * in arch/powerpc/cpu/ppc4xx/start.S |
ca43ba18 HS |
460 | */ |
461 | ||
6d0f6bcf | 462 | #undef CONFIG_SYS_INIT_DCACHE_CS |
ca43ba18 | 463 | /* Where the internal SRAM starts */ |
6d0f6bcf | 464 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR |
ca43ba18 | 465 | /* Where the internal SRAM ends (only offset) */ |
6d0f6bcf | 466 | #define CONFIG_SYS_INIT_RAM_END 0x0F00 |
ca43ba18 HS |
467 | |
468 | /* | |
469 | ||
6d0f6bcf | 470 | CONFIG_SYS_INIT_RAM_ADDR ------> ------------ lower address |
f11033e7 WD |
471 | | | |
472 | | ^ | | |
473 | | | | | |
474 | | | Stack | | |
6d0f6bcf | 475 | CONFIG_SYS_GBL_DATA_OFFSET ----> ------------ |
f11033e7 WD |
476 | | | |
477 | | 64 Bytes | | |
478 | | | | |
6d0f6bcf | 479 | CONFIG_SYS_INIT_RAM_END ------> ------------ higher address |
ca43ba18 HS |
480 | (offset only) |
481 | ||
482 | */ | |
483 | /* size in bytes reserved for initial data */ | |
6d0f6bcf JCPV |
484 | #define CONFIG_SYS_GBL_DATA_SIZE 64 |
485 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
ca43ba18 | 486 | /* Initial value of the stack pointern in internal SRAM */ |
6d0f6bcf | 487 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
ca43ba18 HS |
488 | |
489 | /* | |
490 | * Internal Definitions | |
491 | * | |
492 | * Boot Flags | |
493 | */ | |
494 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
495 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
496 | ||
497 | /* ################################################################################### */ | |
a47a12be | 498 | /* These defines will be used in arch/powerpc/cpu/ppc4xx/cpu_init.c to setup external chip selects */ |
ca43ba18 HS |
499 | /* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ |
500 | ||
501 | /* This chip select accesses the boot device */ | |
502 | /* It depends on boot select switch if this device is 16 or 8 bit */ | |
503 | ||
6d0f6bcf JCPV |
504 | #undef CONFIG_SYS_EBC_PB0AP |
505 | #undef CONFIG_SYS_EBC_PB0CR | |
ca43ba18 | 506 | |
6d0f6bcf JCPV |
507 | #undef CONFIG_SYS_EBC_PB1AP |
508 | #undef CONFIG_SYS_EBC_PB1CR | |
ca43ba18 | 509 | |
6d0f6bcf JCPV |
510 | #undef CONFIG_SYS_EBC_PB2AP |
511 | #undef CONFIG_SYS_EBC_PB2CR | |
ca43ba18 | 512 | |
6d0f6bcf JCPV |
513 | #undef CONFIG_SYS_EBC_PB3AP |
514 | #undef CONFIG_SYS_EBC_PB3CR | |
ca43ba18 | 515 | |
6d0f6bcf JCPV |
516 | #undef CONFIG_SYS_EBC_PB4AP |
517 | #undef CONFIG_SYS_EBC_PB4CR | |
ca43ba18 | 518 | |
6d0f6bcf JCPV |
519 | #undef CONFIG_SYS_EBC_PB5AP |
520 | #undef CONFIG_SYS_EBC_PB5CR | |
ca43ba18 | 521 | |
6d0f6bcf JCPV |
522 | #undef CONFIG_SYS_EBC_PB6AP |
523 | #undef CONFIG_SYS_EBC_PB6CR | |
ca43ba18 | 524 | |
6d0f6bcf JCPV |
525 | #undef CONFIG_SYS_EBC_PB7AP |
526 | #undef CONFIG_SYS_EBC_PB7CR | |
ca43ba18 | 527 | |
6d0f6bcf | 528 | #define CONFIG_SYS_EBC_CFG 0xb84ef000 |
cb482072 | 529 | |
ca43ba18 HS |
530 | #define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */ |
531 | #undef CONFIG_SPD_EEPROM | |
532 | ||
533 | /* | |
534 | * Define this to get more information about system configuration | |
535 | */ | |
536 | /* #define SC3_DEBUGOUT */ | |
537 | #undef SC3_DEBUGOUT | |
538 | ||
539 | /*********************************************************************** | |
540 | * External peripheral base address | |
541 | ***********************************************************************/ | |
542 | ||
6d0f6bcf | 543 | #define CONFIG_SYS_ISA_MEM_BASE_ADDRESS 0x78000000 |
ca43ba18 HS |
544 | /* |
545 |