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281e00a3 WD |
1 | /* |
2 | * Copyright (C) 2003 ETC s.r.o. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License as | |
6 | * published by the Free Software Foundation; either version 2 of | |
7 | * the License, or (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
17 | * MA 02111-1307 USA | |
18 | * | |
19 | * Written by Peter Figuli <peposh@etc.sk>, 2003. | |
20 | * | |
21 | * 2003/13/06 Initial MP10 Support copied from wepep250 | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_ARM920T 1 /* this is an ARM920T CPU */ | |
28 | #define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */ | |
29 | #define CONFIG_SCB9328 1 /* on a scb9328tronix board */ | |
30 | #undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */ | |
31 | ||
32 | #define CONFIG_IMX_SERIAL1 | |
33 | /* | |
34 | * Select serial console configuration | |
35 | */ | |
36 | ||
37 | ||
38 | /* | |
39 | * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if | |
40 | * neccessary in include/cmd_confdefs.h file. (Un)comment for getting | |
41 | * functionality or size of u-boot code. | |
42 | */ | |
43 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | |
44 | & ~CFG_CMD_LOADS \ | |
45 | & ~CFG_CMD_CONSOLE \ | |
46 | & ~CFG_CMD_AUTOSCRIPT \ | |
47 | | CFG_CMD_NET \ | |
48 | | CFG_CMD_PING \ | |
49 | | CFG_CMD_DHCP \ | |
50 | ) | |
51 | ||
52 | #include <cmd_confdefs.h> | |
53 | ||
54 | /* | |
55 | * Boot options. Setting delay to -1 stops autostart count down. | |
56 | * NOTE: Sending parameters to kernel depends on kernel version and | |
57 | * 2.4.19-rmk6-pxa1 patch used while my u-boot coding didn't accept | |
58 | * parameters at all! Do not get confused by them so. | |
59 | */ | |
60 | #define CONFIG_BOOTDELAY -1 | |
61 | #define CONFIG_BOOTARGS "console=ttySMX0,115200n8 root=/dev/mtdblock3 rootfstype=jffs2 mtdparts=scb9328_flash:128k(U-boot)ro,128k(U-boot_env),1m(kernel),4m(root),4m(fs) eval_board=evk9328" | |
62 | #define CONFIG_BOOTCOMMAND "bootm 10040000" | |
63 | #define CONFIG_SHOW_BOOT_PROGRESS | |
64 | #define CONFIG_ETHADDR 80:81:82:83:84:85 | |
65 | #define CONFIG_NETMASK 255.255.255.0 | |
66 | #define CONFIG_IPADDR 10.10.10.9 | |
67 | #define CONFIG_SERVERIP 10.10.10.10 | |
68 | ||
69 | /* | |
70 | * General options for u-boot. Modify to save memory foot print | |
71 | */ | |
72 | #define CFG_LONGHELP /* undef saves memory */ | |
73 | #define CFG_PROMPT "scb9328> " /* prompt string */ | |
74 | #define CFG_CBSIZE 256 /* console I/O buffer */ | |
75 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* print buffer size */ | |
76 | #define CFG_MAXARGS 16 /* max command args */ | |
77 | #define CFG_BARGSIZE CFG_CBSIZE /* boot args buf size */ | |
78 | ||
79 | #define CFG_MEMTEST_START 0x08100000 /* memtest test area */ | |
80 | #define CFG_MEMTEST_END 0x08F00000 | |
81 | ||
82 | #undef CFG_CLKS_IN_HZ /* use HZ for freq. display */ | |
83 | ||
84 | #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ | |
85 | #define CFG_CPUSPEED 0x141 /* core clock - register value */ | |
86 | ||
87 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
88 | #define CONFIG_BAUDRATE 115200 | |
89 | /* | |
90 | * Definitions related to passing arguments to kernel. | |
91 | */ | |
92 | #define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ | |
93 | #define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ | |
94 | #define CONFIG_INITRD_TAG 1 /* send initrd params */ | |
95 | #undef CONFIG_VFD /* do not send framebuffer setup */ | |
96 | ||
97 | ||
98 | /* | |
99 | * Malloc pool need to host env + 128 Kb reserve for other allocations. | |
100 | */ | |
101 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + (128<<10) ) | |
102 | ||
103 | ||
104 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
105 | ||
106 | #define CONFIG_STACKSIZE (120<<10) /* stack size */ | |
107 | ||
108 | #ifdef CONFIG_USE_IRQ | |
109 | #define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */ | |
110 | #define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */ | |
111 | #endif | |
112 | ||
113 | /* SDRAM Setup Values | |
114 | 0x910a8300 Precharge Command CAS 3 | |
115 | 0x910a8200 Precharge Command CAS 2 | |
116 | ||
117 | 0xa10a8300 AutoRefresh Command CAS 3 | |
118 | 0xa10a8200 Set AutoRefresh Command CAS 2 */ | |
119 | ||
120 | #define PRECHARGE_CMD 0x910a8200 | |
121 | #define AUTOREFRESH_CMD 0xa10a8200 | |
281e00a3 WD |
122 | |
123 | /* | |
124 | * SDRAM Memory Map | |
125 | */ | |
126 | /* SH FIXME */ | |
127 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ | |
128 | #define SCB9328_SDRAM_1 0x08000000 /* SDRAM bank #1 */ | |
129 | #define SCB9328_SDRAM_1_SIZE 0x01000000 /* 16 MB */ | |
130 | ||
131 | /* | |
132 | * Flash Controller settings | |
133 | */ | |
134 | ||
135 | /* | |
136 | * Hardware drivers | |
137 | */ | |
138 | ||
139 | ||
140 | /* | |
141 | * Configuration for FLASH memory for the Synertronixx board | |
142 | */ | |
143 | ||
144 | /* #define SCB9328_FLASH_32M */ | |
145 | ||
146 | /* 32MB */ | |
147 | #ifdef SCB9328_FLASH_32M | |
148 | #define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ | |
149 | #define CFG_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */ | |
150 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ | |
151 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
152 | #define SCB9328_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank */ | |
153 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
154 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
155 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
156 | #else | |
157 | ||
158 | /* 16MB */ | |
159 | #define CFG_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/ | |
160 | #define CFG_MAX_FLASH_SECT 128 /* number of sector in FLASH bank */ | |
161 | #define SCB9328_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */ | |
162 | #define SCB9328_FLASH_INTERLEAVE 1 /* ... made of 1 chip */ | |
163 | #define SCB9328_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank */ | |
164 | #define SCB9328_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */ | |
165 | #define SCB9328_FLASH_BASE 0x10000000 /* location of flash memory */ | |
166 | #define SCB9328_FLASH_UNLOCK 1 /* perform hw unlock first */ | |
167 | #endif /* SCB9328_FLASH_32M */ | |
168 | ||
169 | /* This should be defined if CFI FLASH device is present. Actually benefit | |
170 | is not so clear to me. In other words we can provide more informations | |
171 | to user, but this expects more complex flash handling we do not provide | |
172 | now.*/ | |
173 | #undef CFG_FLASH_CFI | |
174 | ||
175 | #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* timeout for Erase operation */ | |
176 | #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* timeout for Write operation */ | |
177 | ||
178 | #define CFG_FLASH_BASE SCB9328_FLASH_BASE | |
179 | ||
180 | /* | |
181 | * This is setting for JFFS2 support in u-boot. | |
182 | * Right now there is no gain for user, but later on booting kernel might be | |
183 | * possible. Consider using XIP kernel running from flash to save RAM | |
184 | * footprint. | |
185 | * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. | |
186 | */ | |
187 | #define CFG_JFFS2_FIRST_BANK 0 | |
188 | #define CFG_JFFS2_FIRST_SECTOR 5 | |
189 | #define CFG_JFFS2_NUM_BANKS 1 | |
190 | ||
191 | /* | |
192 | * Environment setup. Definitions of monitor location and size with | |
193 | * definition of environment setup ends up in 2 possibilities. | |
194 | * 1. Embeded environment - in u-boot code is space for environment | |
195 | * 2. Environment is read from predefined sector of flash | |
196 | * Right now we support 2. possiblity, but expecting no env placed | |
197 | * on mentioned address right now. This also needs to provide whole | |
198 | * sector for it - for us 256Kb is really waste of memory. U-boot uses | |
199 | * default env. and until kernel parameters could be sent to kernel | |
200 | * env. has no sense to us. | |
201 | */ | |
202 | ||
203 | /* Setup for PA23 which is Reset Default PA23 but has to become | |
204 | CS5 */ | |
205 | ||
206 | #define CFG_GPR_A_VAL 0x00800000 | |
207 | #define CFG_GIUS_A_VAL 0x0043fffe | |
208 | ||
209 | #define CFG_MONITOR_BASE 0x10000000 | |
210 | #define CFG_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */ | |
211 | #define CFG_ENV_IS_IN_FLASH 1 | |
212 | #define CFG_ENV_ADDR 0x10020000 /* absolute address for now */ | |
213 | #define CFG_ENV_SIZE 0x20000 | |
214 | ||
215 | #define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */ | |
216 | ||
217 | /* | |
218 | * CSxU_VAL: | |
219 | * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32 | |
220 | * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC | | |
221 | * | |
222 | * CSxL_VAL: | |
223 | * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0 | |
224 | * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN| | |
225 | */ | |
226 | ||
227 | #define CFG_CS0U_VAL 0x000F2000 | |
228 | #define CFG_CS0L_VAL 0x11110d01 | |
229 | #define CFG_CS1U_VAL 0x000F0a00 | |
230 | #define CFG_CS1L_VAL 0x11110601 | |
231 | #define CFG_CS2U_VAL 0x0 | |
232 | #define CFG_CS2L_VAL 0x0 | |
233 | ||
234 | #define CFG_CS3U_VAL 0x000FFFFF | |
235 | #define CFG_CS3L_VAL 0x00000303 | |
236 | ||
237 | #define CFG_CS4U_VAL 0x000F0a00 | |
238 | #define CFG_CS4L_VAL 0x11110301 | |
239 | ||
240 | /* CNC == 3 too long | |
241 | #define CFG_CS5U_VAL 0x0000C210 */ | |
242 | ||
243 | /* #define CFG_CS5U_VAL 0x00008400 | |
244 | mal laenger mahcen, ob der bei 150MHz laenger haelt dann und | |
245 | kaum langsamer ist */ | |
246 | /* #define CFG_CS5U_VAL 0x00009400 | |
247 | #define CFG_CS5L_VAL 0x11010D03 */ | |
248 | ||
249 | #define CFG_CS5U_VAL 0x00008400 | |
250 | #define CFG_CS5L_VAL 0x00000D03 | |
251 | ||
252 | #define CONFIG_DRIVER_DM9000 1 | |
253 | #define CONFIG_DRIVER_DM9000 1 | |
254 | #define CONFIG_DM9000_BASE 0x16000000 | |
255 | #define DM9000_IO CONFIG_DM9000_BASE | |
256 | #define DM9000_DATA (CONFIG_DM9000_BASE+4) | |
257 | /* #define CONFIG_DM9000_USE_8BIT */ | |
258 | #define CONFIG_DM9000_USE_16BIT | |
259 | /* #define CONFIG_DM9000_USE_32BIT */ | |
260 | ||
261 | /* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1) | |
262 | f_ref=16,777MHz | |
263 | ||
264 | 0x002a141f: 191,9944MHz | |
265 | 0x040b2007: 144MHz | |
266 | 0x042a141f: 96MHz | |
267 | 0x0811140d: 64MHz | |
268 | 0x040e200e: 150MHz | |
269 | 0x00321431: 200MHz | |
270 | ||
271 | 0x08001800: 64MHz mit 16er Quarz | |
272 | 0x04001800: 96MHz mit 16er Quarz | |
273 | 0x04002400: 144MHz mit 16er Quarz | |
274 | ||
275 | 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0 | |
276 | |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */ | |
277 | ||
278 | #define CPU200 | |
279 | ||
280 | #ifdef CPU200 | |
281 | #define CFG_MPCTL0_VAL 0x00321431 | |
282 | #else | |
283 | #define CFG_MPCTL0_VAL 0x040e200e | |
284 | #endif | |
285 | ||
286 | /* #define BUS64 */ | |
287 | #define BUS72 | |
288 | ||
289 | #ifdef BUS72 | |
290 | #define CFG_SPCTL0_VAL 0x04002400 | |
291 | #endif | |
292 | ||
293 | #ifdef BUS96 | |
294 | #define CFG_SPCTL0_VAL 0x04001800 | |
295 | #endif | |
296 | ||
297 | #ifdef BUS64 | |
298 | #define CFG_SPCTL0_VAL 0x08001800 | |
299 | #endif | |
300 | ||
301 | /* Das ist der BCLK Divider, der aus der System PLL | |
302 | BCLK und HCLK erzeugt: | |
303 | 31 | xxxx xxxx xxxx xxxx xx10 11xx xxxx xxxx | 0 | |
304 | 0x2f008403 : 192MHz/2=96MHz, 144MHz/2=72MHz PRESC=1->BCLKDIV=2 | |
305 | 0x2f008803 : 192MHz/3=64MHz, 240MHz/3=80MHz PRESC=1->BCLKDIV=2 | |
306 | 0x2f001003 : 192MHz/5=38,4MHz | |
307 | 0x2f000003 : 64MHz/1 | |
308 | Bit 22: SPLL Restart | |
309 | Bit 21: MPLL Restart */ | |
310 | ||
311 | #ifdef BUS64 | |
312 | #define CFG_CSCR_VAL 0x2f030003 | |
313 | #endif | |
314 | ||
315 | #ifdef BUS72 | |
316 | #define CFG_CSCR_VAL 0x2f030403 | |
317 | #endif | |
318 | ||
319 | /* | |
320 | * Well this has to be defined, but on the other hand it is used differently | |
321 | * one may expect. For instance loadb command do not cares :-) | |
322 | * So advice is - do not relay on this... | |
323 | */ | |
324 | #define CFG_LOAD_ADDR 0x08400000 | |
325 | ||
326 | #define MHZ16QUARZINUSE | |
327 | ||
328 | #ifdef MHZ16QUARZINUSE | |
329 | #define CONFIG_SYSPLL_CLK_FREQ 16000000 | |
330 | #else | |
331 | #define CONFIG_SYSPLL_CLK_FREQ 16780000 | |
332 | #endif | |
333 | ||
334 | #define CONFIG_SYS_CLK_FREQ 16780000 | |
335 | ||
336 | /* FMCR Bit 0 becomes 0 to make CS3 CS3 :P */ | |
337 | #define CFG_FMCR_VAL 0x00000001 | |
338 | ||
339 | /* Bit[0:3] contain PERCLK1DIV for UART 1 | |
340 | 0x000b00b ->b<- -> 192MHz/12=16MHz | |
341 | 0x000b00b ->8<- -> 144MHz/09=16MHz | |
342 | 0x000b00b ->3<- -> 64MHz/4=16MHz */ | |
343 | ||
344 | #ifdef BUS96 | |
345 | #define CFG_PCDR_VAL 0x000b00b5 | |
346 | #endif | |
347 | ||
348 | #ifdef BUS64 | |
349 | #define CFG_PCDR_VAL 0x000b00b3 | |
350 | #endif | |
351 | ||
352 | #ifdef BUS72 | |
353 | #define CFG_PCDR_VAL 0x000b00b8 | |
354 | #endif | |
355 | ||
356 | #endif /* __CONFIG_H */ |