[people/ms/u-boot.git] / include / configs / sequoia.h

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * (C) Copyright 2006
 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/************************************************************************
 * sequoia.h - configuration for Sequoia board (PowerPC440EPx)
 ***********************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_SEQUOIA		1		/* Board is Sequoia	*/
#define CONFIG_440EPX		1		/* Specific PPC440EPx	*/
#define CONFIG_4xx		1		/* ... PPC4xx family	*/
#define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/

#define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
#define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN		(384 * 1024)	/* Reserve 384 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/

#define CFG_BOOT_BASE_ADDR	0xf0000000
#define CFG_SDRAM_BASE		0x00000000	/* _must_ be 0		*/
#define CFG_FLASH_BASE		0xfe000000	/* start of FLASH	*/
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_NAND_ADDR		0xd0000000      /* NAND Flash		*/
#define CFG_OCM_BASE		0xe0010000      /* ocm			*/
#define CFG_PCI_BASE		0xe0000000      /* Internal PCI regs	*/
#define CFG_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
#define CFG_PCI_MEMBASE1	CFG_PCI_MEMBASE  + 0x10000000
#define CFG_PCI_MEMBASE2	CFG_PCI_MEMBASE1 + 0x10000000
#define CFG_PCI_MEMBASE3	CFG_PCI_MEMBASE2 + 0x10000000

/* Don't change either of these */
#define CFG_PERIPHERAL_BASE	0xef600000	/* internal peripherals	*/

#define CFG_USB2D0_BASE		0xe0000100
#define CFG_USB_DEVICE		0xe0000000
#define CFG_USB_HOST		0xe0000400
#define CFG_BCSR_BASE		0xc0000000

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer
 *----------------------------------------------------------------------*/
#if 0
/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache	*/
#define CFG_INIT_RAM_DCACHE	1		/* d-cache as init ram	*/
#define CFG_INIT_RAM_ADDR	0x70000000	/* DCache		*/
#else
#define CFG_INIT_RAM_OCM	1		/* OCM as init ram	*/
#define CFG_INIT_RAM_ADDR	CFG_OCM_BASE	/* OCM			*/
#endif

#define CFG_INIT_RAM_END	(4 << 10)
#define CFG_GBL_DATA_SIZE	256		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CFG_EXT_SERIAL_CLOCK	11059200	/* ext. 11.059MHz clk	*/
#define CONFIG_BAUDRATE		115200
#define CONFIG_SERIAL_MULTI     1
/* define this if you want console on UART1 */
#undef CONFIG_UART1_CONSOLE

#define CFG_BAUDRATE_TABLE						\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
/*
 * Define here the location of the environment variables (FLASH or EEPROM).
 * Note: DENX encourages to use redundant environment in FLASH.
 */
#if 1 /* test-only */
#define CFG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/
#else
#define CFG_ENV_IS_IN_NAND	1	/* use NAND for environment vars	*/
#endif
#if 0
#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars	*/
#endif

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/

#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }

#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	512	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/
#define CFG_FLASH_PROTECTION	1	/* use hardware flash protection	*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash	*/

#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE	0x20000 	/* size of one complete sector	*/
#define CFG_ENV_ADDR		((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * NAND FLASH
 *----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1
#define CFG_NAND_BASE		CFG_NAND_ADDR

/*
 * IPL (Initial Program Loader, integrated inside CPU)
 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 *
 * SPL (Secondary Program Loader)
 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 * controller and the NAND controller so that the special U-Boot image can be
 * loaded from NAND to SDRAM.
 *
 * NUB (NAND U-Boot)
 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 *
 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
 * set up. While still running from cache, I experienced problems accessing
 * the NAND controller.	sr - 2006-08-25
 */
#define CFG_NAND_BOOT_SPL_SRC	0xfffff000	/* SPL location			*/
#define CFG_NAND_BOOT_SPL_SIZE	(4 << 10)	/* SPL size			*/
#define CFG_NAND_BOOT_SPL_DST	(CFG_OCM_BASE + (12 << 10)) /* Copy SPL here	*/
#define CFG_NAND_U_BOOT_DST	0x01000000	/* Load NUB to this addr	*/
#define CFG_NAND_U_BOOT_START	CFG_NAND_U_BOOT_DST /* Start NUB from this addr	*/
#define CFG_NAND_BOOT_SPL_DELTA	(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)

/*
 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 */
#define CFG_NAND_U_BOOT_OFFS	(16 << 10)	/* Offset to RAM U-Boot image	*/
#define CFG_NAND_U_BOOT_SIZE	(384 << 10)	/* Size of RAM U-Boot image	*/

/*
 * Now the NAND chip has to be defined (no autodetection used!)
 */
#define CFG_NAND_PAGE_SIZE	(512)		/* NAND chip page size		*/
#define CFG_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size		*/
#define CFG_NAND_PAGE_COUNT	(32)		/* NAND chip page count		*/
#define CFG_NAND_BAD_BLOCK_POS	(5)		/* Location of bad block marker	*/
#undef CFG_NAND_4_ADDR_CYCLE			/* No fourth addr used (<=32MB)	*/

#ifdef CFG_ENV_IS_IN_NAND
#define CFG_ENV_SIZE		0x4000
#define CFG_ENV_OFFSET		(CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE)
#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET + CFG_ENV_SIZE)
#endif

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#define CFG_MBYTES_SDRAM        (256)    /* 256MB			*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_HARD_I2C		1		/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C				/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000		/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_MULTI_EEPROMS
#define CFG_I2C_EEPROM_ADDR	(0xa8>>1)
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10

#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_SIZE		0x200		/* Size of Environment vars	*/
#define CFG_ENV_OFFSET		0x0
#endif /* CFG_ENV_IS_IN_EEPROM */

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
#define CONFIG_DTT_AD7414	1		/* use AD7414		*/
#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
#define CFG_DTT_MAX_TEMP	70
#define CFG_DTT_LOW_TEMP	-30
#define CFG_DTT_HYSTERESIS	3

#define CONFIG_PREBOOT	"echo;"						\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"hostname=sequoia\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
	"flash_nfs=run nfsargs addip addtty;"				\
		"bootm ${kernel_addr}\0"				\
	"flash_self=run ramargs addip addtty;"				\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
	        "bootm\0"						\
	"rootpath=/opt/eldk/ppc_4xx\0"					\
	"bootfile=/tftpboot/sequoia/uImage\0"				\
	"kernel_addr=FE000000\0"					\
	"ramdisk_addr=FE180000\0"					\
	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0"		\
	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"	\
		"cp.b 100000 FFFA0000 60000\0"			        \
	"upd=run load;run update\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_M88E1111_PHY	1
#define	CONFIG_IBM_EMAC4_V4	1
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address, See schematics	*/

#define CONFIG_PHY_RESET        1	/* reset phy upon startup         */
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CFG_RX_ETH_BUFFER	32	/* Number of ethernet rx buffers & descriptors */

#define CONFIG_NET_MULTI	1
#define CONFIG_HAS_ETH1		1	/* add support for "eth1addr"	*/
#define CONFIG_PHY1_ADDR	1

/* USB */
#define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE

/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

#define CONFIG_COMMANDS       (CONFIG_CMD_DFL	|	\
			       CFG_CMD_ASKENV	|	\
			       CFG_CMD_DHCP	|	\
			       CFG_CMD_DTT	|	\
			       CFG_CMD_DIAG	|	\
			       CFG_CMD_EEPROM	|	\
			       CFG_CMD_ELF	|	\
			       CFG_CMD_FAT	|	\
			       CFG_CMD_I2C	|	\
			       CFG_CMD_IRQ	|	\
			       CFG_CMD_MII	|	\
			       CFG_CMD_NAND	|	\
			       CFG_CMD_NET	|	\
			       CFG_CMD_NFS	|	\
			       CFG_CMD_PCI	|	\
			       CFG_CMD_PING	|	\
			       CFG_CMD_REGINFO	|	\
			       CFG_CMD_SDRAM	|	\
			       CFG_CMD_USB    )

#define CONFIG_SUPPORT_VFAT

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*-----------------------------------------------------------------------
 * Miscellaneous configurable options
 *----------------------------------------------------------------------*/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	        "=> "	/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	        1024	/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	        256	/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	        16	/* max number of command args	*/
#define CFG_BARGSIZE	        CFG_CBSIZE /* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000 /* memtest works on		*/
#define CFG_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000  /* default load address	*/
#define CFG_EXTBDINFO		1	/* To use extended board_into (bd_t) */

#define CFG_HZ		        1000	/* decrementer freq: 1 ms ticks	*/

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_LOOPW            1       /* enable loopw command         */
#define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1	/* include version env variable */

/*-----------------------------------------------------------------------
 * PCI stuff
 *----------------------------------------------------------------------*/
/* General PCI */
#define CONFIG_PCI			/* include pci support	        */
#define CONFIG_PCI_PNP			/* do (not) pci plug-and-play   */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup  */
#define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/

/* Board-specific PCI */
#define CFG_PCI_PRE_INIT		/* enable board pci_pre_init()	*/
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

#define CFG_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC				*/
#define CFG_PCI_SUBSYS_ID       0xcafe	/* Whatever			*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 *----------------------------------------------------------------------*/
#define CFG_FLASH		CFG_FLASH_BASE
#define CFG_NAND		0xD0000000
#define CFG_CPLD		0xC0000000

/*
 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 */
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CFG_NAND_CS		3		/* NAND chip connected to CSx	*/
/* Memory Bank 0 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x03017300
#define CFG_EBC_PB0CR		(CFG_FLASH | 0xba000)

/* Memory Bank 3 (NAND-FLASH) initialization					*/
#define CFG_EBC_PB3AP		0x018003c0
#define CFG_EBC_PB3CR		(CFG_NAND | 0x1c000)
#else
#define CFG_NAND_CS		0		/* NAND chip connected to CSx	*/
/* Memory Bank 3 (NOR-FLASH) initialization					*/
#define CFG_EBC_PB3AP		0x03017300
#define CFG_EBC_PB3CR		(CFG_FLASH | 0xba000)

/* Memory Bank 0 (NAND-FLASH) initialization					*/
#define CFG_EBC_PB0AP		0x018003c0
#define CFG_EBC_PB0CR		(CFG_NAND | 0x1c000)
#endif

/* Memory Bank 2 (CPLD) initialization						*/
#define CFG_EBC_PB2AP		0x24814580
#define CFG_EBC_PB2CR		(CFG_CPLD | 0x38000)

/*-----------------------------------------------------------------------
 * Cache Configuration
 *----------------------------------------------------------------------*/
#define CFG_DCACHE_SIZE		(32<<10)  /* For AMCC 440 CPUs			*/
#define CFG_CACHELINE_SIZE	32	      /* ...			            */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	      /* log base 2 of the above value	*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	    /* which serial port to use */
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
887e2ec9 SR	1	/*
	2	* (C) Copyright 2006
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* (C) Copyright 2006
	6	* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
	7	* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/************************************************************************
	26	* sequoia.h - configuration for Sequoia board (PowerPC440EPx)
	27	***********************************************************************/
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*-----------------------------------------------------------------------
	32	* High Level Configuration Options
	33	----------------------------------------------------------------------/
	34	#define CONFIG_SEQUOIA 1 /* Board is Sequoia */
	35	#define CONFIG_440EPX 1 /* Specific PPC440EPx */
	36	#define CONFIG_4xx 1 /* ... PPC4xx family */
	37	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
	38
	39	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
	40	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	41
	42	/*-----------------------------------------------------------------------
	43	* Base addresses -- Note these are effective addresses where the
	44	* actual resources get mapped (not physical addresses)
	45	----------------------------------------------------------------------/
	46	#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
	47	#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
	48
	49	#define CFG_BOOT_BASE_ADDR 0xf0000000
	50	#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
	51	#define CFG_FLASH_BASE 0xfe000000 /* start of FLASH */
	52	#define CFG_MONITOR_BASE TEXT_BASE
	53	#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
	54	#define CFG_OCM_BASE 0xe0010000 /* ocm */
	55	#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
	56	#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
	57	#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
	58	#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
	59	#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
	60
	61	/* Don't change either of these */
	62	#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
	63
	64	#define CFG_USB2D0_BASE 0xe0000100
65	#define CFG_USB_DEVICE 0xe0000000
66	#define CFG_USB_HOST 0xe0000400
67	#define CFG_BCSR_BASE 0xc0000000
68
69	/*-----------------------------------------------------------------------
70	* Initial RAM & stack pointer
71	----------------------------------------------------------------------/
72	#if 0
73	/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
74	#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
75	#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
76	#else
77	#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */
78	#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
79	#endif
80
81	#define CFG_INIT_RAM_END (4 << 10)
82	#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
83	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
84	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
85
86	/*-----------------------------------------------------------------------
87	* Serial Port
88	----------------------------------------------------------------------/
89	#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
90	#define CONFIG_BAUDRATE 115200
91	#define CONFIG_SERIAL_MULTI 1
92	/* define this if you want console on UART1 */
93	#undef CONFIG_UART1_CONSOLE
94
95	#define CFG_BAUDRATE_TABLE \
96	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
97
98	/*-----------------------------------------------------------------------
99	* Environment
100	----------------------------------------------------------------------/
101	/*
102	* Define here the location of the environment variables (FLASH or EEPROM).
103	* Note: DENX encourages to use redundant environment in FLASH.
104	*/
105	#if 1 /* test-only */
106	#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
107	#else
108	#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
109	#endif
110	#if 0
111	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
112	#endif
113
114	/*-----------------------------------------------------------------------
115	* FLASH related
116	----------------------------------------------------------------------/
117	#define CFG_FLASH_CFI /* The flash is CFI compatible */
118	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
119
120	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
121
122	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
123	#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
124
125	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
126	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
127
128	#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
129	#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
130
131	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
132	#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
133
134	#ifdef CFG_ENV_IS_IN_FLASH
135	#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
136	#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
137	#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
138
139	/* Address and size of Redundant Environment Sector */
140	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
141	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
142	#endif
143
144	/*-----------------------------------------------------------------------
145	* NAND FLASH
146	----------------------------------------------------------------------/
147	#define CFG_MAX_NAND_DEVICE 1
148	#define NAND_MAX_CHIPS 1
149	#define CFG_NAND_BASE CFG_NAND_ADDR
150
151	/*
152	* IPL (Initial Program Loader, integrated inside CPU)
153	* Will load first 4k from NAND (SPL) into cache and execute it from there.
154	*
155	* SPL (Secondary Program Loader)
156	* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
157	* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
158	* controller and the NAND controller so that the special U-Boot image can be
159	* loaded from NAND to SDRAM.
160	*
161	* NUB (NAND U-Boot)
162	* This NAND U-Boot (NUB) is a special U-Boot version which can be started
163	* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
164	*
165	* On 440EPx the SPL is copied to SDRAM before the NAND controller is
166	* set up. While still running from cache, I experienced problems accessing
167	* the NAND controller. sr - 2006-08-25
168	*/
169	#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
170	#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
171	#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
172	#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
173	#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
174	#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
175
176	/*
177	* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
178	*/
179	#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
180	#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
181
182	/*
183	* Now the NAND chip has to be defined (no autodetection used!)
184	*/
185	#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
186	#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
187	#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
188	#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
189	#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
190
191	#ifdef CFG_ENV_IS_IN_NAND
192	#define CFG_ENV_SIZE 0x4000
193	#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_NAND_U_BOOT_SIZE)
194	#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
195	#endif
196
197	/*-----------------------------------------------------------------------
198	* DDR SDRAM
199	----------------------------------------------------------------------/
200	#define CFG_MBYTES_SDRAM (256) /* 256MB */
201
202	/*-----------------------------------------------------------------------
203	* I2C
204	----------------------------------------------------------------------/
205	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
206	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
207	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
208	#define CFG_I2C_SLAVE 0x7F
209
210	#define CFG_I2C_MULTI_EEPROMS
211	#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
212	#define CFG_I2C_EEPROM_ADDR_LEN 1
213	#define CFG_EEPROM_PAGE_WRITE_ENABLE
214	#define CFG_EEPROM_PAGE_WRITE_BITS 3
215	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
216
217	#ifdef CFG_ENV_IS_IN_EEPROM
218	#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */
219	#define CFG_ENV_OFFSET 0x0
220	#endif /* CFG_ENV_IS_IN_EEPROM */
221
222	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
223	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
224	#define CONFIG_DTT_AD7414 1 /* use AD7414 */
225	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
226	#define CFG_DTT_MAX_TEMP 70
227	#define CFG_DTT_LOW_TEMP -30
228	#define CFG_DTT_HYSTERESIS 3
229
230	#define CONFIG_PREBOOT "echo;" \
231	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
232	"echo"
233
234	#undef CONFIG_BOOTARGS
235
236	#define CONFIG_EXTRA_ENV_SETTINGS \
237	"netdev=eth0\0" \
238	"hostname=sequoia\0" \
239	"nfsargs=setenv bootargs root=/dev/nfs rw " \
240	"nfsroot=${serverip}:${rootpath}\0" \
241	"ramargs=setenv bootargs root=/dev/ram rw\0" \
242	"addip=setenv bootargs ${bootargs} " \
243	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
244	":${hostname}:${netdev}:off panic=1\0" \
245	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
246	"flash_nfs=run nfsargs addip addtty;" \
247	"bootm ${kernel_addr}\0" \
248	"flash_self=run ramargs addip addtty;" \
249	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
250	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
251	"bootm\0" \
252	"rootpath=/opt/eldk/ppc_4xx\0" \
253	"bootfile=/tftpboot/sequoia/uImage\0" \
254	"kernel_addr=FE000000\0" \
255	"ramdisk_addr=FE180000\0" \
256	"load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \
257	"update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
258	"cp.b 100000 FFFA0000 60000\0" \
259	"upd=run load;run update\0" \
260	""
261	#define CONFIG_BOOTCOMMAND "run flash_self"
262
263	#if 0
264	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
265	#else
266	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
267	#endif
268
269	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
270	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
271
272	#define CONFIG_M88E1111_PHY 1
273	#define CONFIG_IBM_EMAC4_V4 1
274	#define CONFIG_MII 1 /* MII PHY management */
275	#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
276
277	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
278	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
279
280	#define CONFIG_HAS_ETH0
281	#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
282
283	#define CONFIG_NET_MULTI 1
284	#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
285	#define CONFIG_PHY1_ADDR 1
286
287	/* USB */
288	#define CONFIG_USB_OHCI
289	#define CONFIG_USB_STORAGE
290
291	/* Comment this out to enable USB 1.1 device */
292	#define USB_2_0_DEVICE
293
294	/* Partitions */
295	#define CONFIG_MAC_PARTITION
296	#define CONFIG_DOS_PARTITION
297	#define CONFIG_ISO_PARTITION
298
299	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
300	CFG_CMD_ASKENV \| \
301	CFG_CMD_DHCP \| \
302	CFG_CMD_DTT \| \
303	CFG_CMD_DIAG \| \
304	CFG_CMD_EEPROM \| \
305	CFG_CMD_ELF \| \
306	CFG_CMD_FAT \| \
307	CFG_CMD_I2C \| \
308	CFG_CMD_IRQ \| \
309	CFG_CMD_MII \| \
310	CFG_CMD_NAND \| \
311	CFG_CMD_NET \| \
312	CFG_CMD_NFS \| \
313	CFG_CMD_PCI \| \
314	CFG_CMD_PING \| \
315	CFG_CMD_REGINFO \| \
316	CFG_CMD_SDRAM \| \
317	CFG_CMD_USB )
318
319	#define CONFIG_SUPPORT_VFAT
320
321	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
322	#include <cmd_confdefs.h>
323
324	/*-----------------------------------------------------------------------
325	* Miscellaneous configurable options
326	----------------------------------------------------------------------/
327	#define CFG_LONGHELP /* undef to save memory */
328	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
329	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
330	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
331	#else
332	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
333	#endif
334	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
335	#define CFG_MAXARGS 16 /* max number of command args */
336	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
337
338	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
339	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
340
341	#define CFG_LOAD_ADDR 0x100000 /* default load address */
342	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
343
344	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
345
346	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
347	#define CONFIG_LOOPW 1 /* enable loopw command */
348	#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
349	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
350	#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
351
352	/*-----------------------------------------------------------------------
353	* PCI stuff
354	----------------------------------------------------------------------/
355	/* General PCI */
356	#define CONFIG_PCI /* include pci support */
357	#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
358	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
359	#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
360
361	/* Board-specific PCI */
362	#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
363	#define CFG_PCI_TARGET_INIT
364	#define CFG_PCI_MASTER_INIT
365
366	#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
367	#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
368
369	/*
370	* For booting Linux, the board info and command line data
371	* have to be in the first 8 MB of memory, since this is
372	* the maximum mapped by the Linux kernel during initialization.
373	*/
374	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
375
376	/*-----------------------------------------------------------------------
377	* External Bus Controller (EBC) Setup
378	----------------------------------------------------------------------/
379	#define CFG_FLASH CFG_FLASH_BASE
380	#define CFG_NAND 0xD0000000
381	#define CFG_CPLD 0xC0000000
382
383	/*
384	* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
385	*/
386	#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
387	#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
388	/* Memory Bank 0 (NOR-FLASH) initialization */
389	#define CFG_EBC_PB0AP 0x03017300
390	#define CFG_EBC_PB0CR (CFG_FLASH \| 0xba000)
391
392	/* Memory Bank 3 (NAND-FLASH) initialization */
393	#define CFG_EBC_PB3AP 0x018003c0
394	#define CFG_EBC_PB3CR (CFG_NAND \| 0x1c000)
395	#else
396	#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
397	/* Memory Bank 3 (NOR-FLASH) initialization */
398	#define CFG_EBC_PB3AP 0x03017300
399	#define CFG_EBC_PB3CR (CFG_FLASH \| 0xba000)
400
401	/* Memory Bank 0 (NAND-FLASH) initialization */
402	#define CFG_EBC_PB0AP 0x018003c0
403	#define CFG_EBC_PB0CR (CFG_NAND \| 0x1c000)
404	#endif
405
406	/* Memory Bank 2 (CPLD) initialization */
407	#define CFG_EBC_PB2AP 0x24814580
408	#define CFG_EBC_PB2CR (CFG_CPLD \| 0x38000)
409
410	/*-----------------------------------------------------------------------
411	* Cache Configuration
412	----------------------------------------------------------------------/
413	#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */
414	#define CFG_CACHELINE_SIZE 32 /* ... */
415	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
416	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
417	#endif
418
419	/*
420	* Internal Definitions
421	*
422	* Boot Flags
423	*/
424	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
425	#define BOOTFLAG_WARM 0x02 /* Software reboot */
426
427	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
428	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
429	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
430	#endif
431	#endif /* __CONFIG_H */