[people/ms/u-boot.git] / include / configs / sh7753evb.h

/*
 * Configuation settings for the sh7753evb board
 *
 * Copyright (C) 2012 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SH7753EVB_H
#define __SH7753EVB_H

#define CONFIG_CPU_SH7753	1
#define CONFIG_SH7753EVB	1

#define CONFIG_SYS_TEXT_BASE	0x5ff80000

#define CONFIG_CMD_DFL
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"

#define CONFIG_DISPLAY_BOARDINFO
#undef	CONFIG_SHOW_BOOT_PROGRESS
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/* MEMORY */
#define SH7753EVB_SDRAM_BASE		(0x40000000)
#define SH7753EVB_SDRAM_SIZE		(512 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF2	1

#define CONFIG_SYS_MEMTEST_START	(SH7753EVB_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					 480 * 1024 * 1024)
#undef	CONFIG_SYS_ALT_MEMTEST
#undef	CONFIG_SYS_MEMTEST_SCRATCH
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE		(SH7753EVB_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE		(SH7753EVB_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
					 128 * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* Ether */
#define CONFIG_SH_ETHER			1
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	18
#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
#define CONFIG_SH_ETHER_USE_GETHER	1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
#define CONFIG_PHY_VITESSE

#define SH7753EVB_ETHERNET_MAC_BASE_SPI	0x00090000
#define SH7753EVB_SPI_SECTOR_SIZE	(64 * 1024)
#define SH7753EVB_ETHERNET_MAC_BASE	SH7753EVB_ETHERNET_MAC_BASE_SPI
#define SH7753EVB_ETHERNET_MAC_SIZE	17
#define SH7753EVB_ETHERNET_NUM_CH	2

/* SPI */
#define CONFIG_SH_SPI			1
#define CONFIG_SH_SPI_BASE		0xfe002000

/* MMCIF */
#define CONFIG_SH_MMCIF			1
#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
#define CONFIG_SH_MMCIF_CLK		48000000

/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_ADDR		(0x00080000)
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS				\
		"netboot=bootp; bootm\0"

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV	4
#endif	/* __SH7753EVB_H */
Commit	Line	Data
320cf350 YS	1	/*
	2	* Configuation settings for the sh7753evb board
	3	*
	4	* Copyright (C) 2012 Renesas Solutions Corp.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __SH7753EVB_H
	10	#define __SH7753EVB_H
	11
320cf350 YS	12	#define CONFIG_CPU_SH7753 1
	13	#define CONFIG_SH7753EVB 1
	14
	15	#define CONFIG_SYS_TEXT_BASE 0x5ff80000
320cf350	16
320cf350 YS	17	#define CONFIG_CMD_DFL
320cf350 YS	18	#define CONFIG_CMD_SDRAM
320cf350 YS	19	#define CONFIG_CMD_MD5SUM
320cf350 YS	20	#define CONFIG_MD5
320cf350 YS	21
320cf350 YS	22	#define CONFIG_BAUDRATE 115200
320cf350 YS	23	#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
320cf350 YS	24
18a40e84	25	#define CONFIG_DISPLAY_BOARDINFO
320cf350 YS	26	#undef CONFIG_SHOW_BOOT_PROGRESS
	27	#define CONFIG_CMDLINE_EDITING
	28	#define CONFIG_AUTO_COMPLETE
	29
	30	/* MEMORY */
	31	#define SH7753EVB_SDRAM_BASE (0x40000000)
	32	#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
	33
	34	#define CONFIG_SYS_LONGHELP
	35	#define CONFIG_SYS_CBSIZE 256
	36	#define CONFIG_SYS_PBSIZE 256
	37	#define CONFIG_SYS_MAXARGS 16
	38	#define CONFIG_SYS_BARGSIZE 512
	39	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	40
	41	/* SCIF */
	42	#define CONFIG_SCIF_CONSOLE 1
	43	#define CONFIG_CONS_SCIF2 1
320cf350 YS	44
	45	#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
	46	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	47	480 * 1024 * 1024)
	48	#undef CONFIG_SYS_ALT_MEMTEST
	49	#undef CONFIG_SYS_MEMTEST_SCRATCH
	50	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	51
	52	#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
	53	#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
	54	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
	55	128 * 1024 * 1024)
	56
	57	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	58	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	59	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	60	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	61
320cf350 YS	62	/* Ether */
	63	#define CONFIG_SH_ETHER 1
	64	#define CONFIG_SH_ETHER_USE_PORT 0
	65	#define CONFIG_SH_ETHER_PHY_ADDR 18
	66	#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
	67	#define CONFIG_SH_ETHER_USE_GETHER 1
	68	#define CONFIG_PHYLIB
	69	#define CONFIG_BITBANGMII
	70	#define CONFIG_BITBANGMII_MULTI
	71	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
	72	#define CONFIG_PHY_VITESSE
	73
	74	#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
	75	#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
	76	#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
	77	#define SH7753EVB_ETHERNET_MAC_SIZE 17
	78	#define SH7753EVB_ETHERNET_NUM_CH 2
320cf350 YS	79
	80	/* SPI */
	81	#define CONFIG_SH_SPI 1
	82	#define CONFIG_SH_SPI_BASE 0xfe002000
320cf350 YS	83
320cf350 YS	84	/* MMCIF */
320cf350 YS	85	#define CONFIG_SH_MMCIF 1
	86	#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
	87	#define CONFIG_SH_MMCIF_CLK 48000000
	88
	89	/* ENV setting */
	90	#define CONFIG_ENV_IS_EMBEDDED
	91	#define CONFIG_ENV_IS_IN_SPI_FLASH
	92	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	93	#define CONFIG_ENV_ADDR (0x00080000)
	94	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
	95	#define CONFIG_ENV_OVERWRITE 1
	96	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	97	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	98	#define CONFIG_EXTRA_ENV_SETTINGS \
	99	"netboot=bootp; bootm\0"
	100
	101	/* Board Clock */
	102	#define CONFIG_SYS_CLK_FREQ 48000000
	103	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
	104	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
	105	#define CONFIG_SYS_TMU_CLK_DIV 4
	106	#endif /* __SH7753EVB_H */