[people/ms/u-boot.git] / include / configs / sh7757lcr.h

/*
 * Configuation settings for the sh7757lcr board
 *
 * Copyright (C) 2011 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SH7757LCR_H
#define __SH7757LCR_H

#define CONFIG_CPU_SH7757	1
#define CONFIG_SH7757LCR_DDR_ECC	1

#define CONFIG_DISPLAY_BOARDINFO
#undef	CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define SH7757LCR_SDRAM_BASE		(0x80000000)
#define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
#define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
#define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)

#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_CONS_SCIF2	1

#define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					 224 * 1024 * 1024)
#undef	CONFIG_SYS_ALT_MEMTEST
#undef	CONFIG_SYS_MEMTEST_SCRATCH
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
					 (128 + 16) * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

#define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
#define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
#define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
#define SH7757LCR_ETHERNET_MAC_SIZE	17
#define SH7757LCR_ETHERNET_NUM_CH	2

/* Gigabit Ether */
#define SH7757LCR_GIGA_ETHERNET_NUM_CH	2

/* SPI */
#define CONFIG_SH_SPI_BASE		0xfe002000

/* MMCIF */
#define CONFIG_SH_MMCIF			1
#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
#define CONFIG_SH_MMCIF_CLK		48000000

/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
#define SH7757LCR_GRA_OFFSET		0x1f000000
#define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
#define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
#define SH7757LCR_PCIEBRG_ADDR		0x00090000
#define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)

/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_ADDR		(0x00080000)
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS				\
		"netboot=bootp; bootm\0"

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV	4
#endif	/* __SH7757LCR_H */
Commit	Line	Data
8e9c897b YS	1	/*
	2	* Configuation settings for the sh7757lcr board
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
8e9c897b YS	7	*/
	8
	9	#ifndef __SH7757LCR_H
	10	#define __SH7757LCR_H
	11
8e9c897b	12	#define CONFIG_CPU_SH7757 1
3ed81645	13	#define CONFIG_SH7757LCR_DDR_ECC 1
8e9c897b	14
18a40e84	15	#define CONFIG_DISPLAY_BOARDINFO
8e9c897b YS	16	#undef CONFIG_SHOW_BOOT_PROGRESS
	17
	18	/* MEMORY */
	19	#define SH7757LCR_SDRAM_BASE (0x80000000)
	20	#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
	21	#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
	22	#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
	23
8e9c897b	24	#define CONFIG_SYS_PBSIZE 256
8e9c897b YS	25	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	26
	27	/* SCIF */
8e9c897b	28	#define CONFIG_CONS_SCIF2 1
8e9c897b YS	29
	30	#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
	31	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	32	224 * 1024 * 1024)
	33	#undef CONFIG_SYS_ALT_MEMTEST
	34	#undef CONFIG_SYS_MEMTEST_SCRATCH
	35	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	36
	37	#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
	38	#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
	39	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
	40	(128 + 16) * 1024 * 1024)
	41
	42	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	43	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	44	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	45	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	46
8e9c897b	47	/* Ether */
8e9c897b YS	48	#define CONFIG_SH_ETHER_USE_PORT 0
	49	#define CONFIG_SH_ETHER_PHY_ADDR 1
	50	#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
0c2a37a5 YS	51	#define CONFIG_BITBANGMII
0c2a37a5 YS	52	#define CONFIG_BITBANGMII_MULTI
a80a6619	53	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
8e9c897b YS	54
	55	#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
	56	#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
	57	#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
	58	#define SH7757LCR_ETHERNET_MAC_SIZE 17
	59	#define SH7757LCR_ETHERNET_NUM_CH 2
8e9c897b YS	60
	61	/* Gigabit Ether */
	62	#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
	63
	64	/* SPI */
8e9c897b	65	#define CONFIG_SH_SPI_BASE 0xfe002000
8e9c897b	66
566f63d5	67	/* MMCIF */
566f63d5 YS	68	#define CONFIG_SH_MMCIF 1
	69	#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
	70	#define CONFIG_SH_MMCIF_CLK 48000000
	71
8e9c897b YS	72	/* SH7757 board */
	73	#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
	74	#define SH7757LCR_GRA_OFFSET 0x1f000000
	75	#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
	76	#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
	77	#define SH7757LCR_PCIEBRG_ADDR 0x00090000
	78	#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
	79
	80	/* ENV setting */
	81	#define CONFIG_ENV_IS_EMBEDDED
8e9c897b YS	82	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	83	#define CONFIG_ENV_ADDR (0x00080000)
	84	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
	85	#define CONFIG_ENV_OVERWRITE 1
	86	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	87	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	88	#define CONFIG_EXTRA_ENV_SETTINGS \
	89	"netboot=bootp; bootm\0"
	90
	91	/* Board Clock */
	92	#define CONFIG_SYS_CLK_FREQ 48000000
684a501e NI	93	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	94	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8e9c897b	95	#define CONFIG_SYS_TMU_CLK_DIV 4
8e9c897b	96	#endif /* __SH7757LCR_H */