[people/ms/u-boot.git] / include / configs / sh7785lcr.h

/*
 * Configuation settings for the Renesas Technology R0P7785LC0011RL board
 *
 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SH7785LCR_H
#define __SH7785LCR_H

#define CONFIG_CPU_SH7785	1

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"bootdevice=0:1\0"						\
	"usbload=usb reset;usbboot;usb stop;bootm\0"

#define CONFIG_DISPLAY_BOARDINFO
#undef	CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#if defined(CONFIG_SH_32BIT)
/* 0x40000000 - 0x47FFFFFF does not use */
#define CONFIG_SH_SDRAM_OFFSET		(0x8000000)
#define SH7785LCR_SDRAM_PHYS_BASE	(0x40000000 + CONFIG_SH_SDRAM_OFFSET)
#define SH7785LCR_SDRAM_BASE		(0x80000000 + CONFIG_SH_SDRAM_OFFSET)
#define SH7785LCR_SDRAM_SIZE		(384 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1		(0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE	(64 * 1024 * 1024)
#define SH7785LCR_USB_BASE		(0xa6000000)
#else
#define SH7785LCR_SDRAM_BASE		(0x08000000)
#define SH7785LCR_SDRAM_SIZE		(128 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1		(0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE	(64 * 1024 * 1024)
#define SH7785LCR_USB_BASE		(0xb4000000)
#endif

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_CONS_SCIF1	1
#define CONFIG_SCIF_EXT_CLOCK	1

#define CONFIG_SYS_MEMTEST_START	(SH7785LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					(SH7785LCR_SDRAM_SIZE) - \
					 4 * 1024 * 1024)
#undef	CONFIG_SYS_ALT_MEMTEST
#undef	CONFIG_SYS_MEMTEST_SCRATCH
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE	(SH7785LCR_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE	(SH7785LCR_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE	(SH7785LCR_FLASH_BASE_1)
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#undef	CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BASE		(SH7785LCR_FLASH_BASE_1)
#define CONFIG_SYS_MAX_FLASH_SECT	512

#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE + \
				 (0 * SH7785LCR_FLASH_BANK_SIZE) }

#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

#undef	CONFIG_SYS_FLASH_PROTECTION
#undef	CONFIG_SYS_DIRECT_FLASH_TFTP

/* R8A66597 */
#define CONFIG_USB_R8A66597_HCD
#define CONFIG_R8A66597_BASE_ADDR	SH7785LCR_USB_BASE
#define CONFIG_R8A66597_XTAL		0x0000	/* 12MHz */
#define CONFIG_R8A66597_LDRV		0x8000	/* 3.3V */
#define CONFIG_R8A66597_ENDIAN		0x0000	/* little */

/* PCI Controller */
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#if defined(CONFIG_SH_32BIT)
#define CONFIG_SH7780_PCI_LSR	0x1ff00001
#define CONFIG_SH7780_PCI_LAR	0x5f000000
#define CONFIG_SH7780_PCI_BAR	0x5f000000
#else
#define CONFIG_SH7780_PCI_LSR	0x07f00001
#define CONFIG_SH7780_PCI_LAR	CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR	CONFIG_SYS_SDRAM_SIZE
#endif
#define CONFIG_PCI_SCAN_SHOW	1

#define CONFIG_PCI_MEM_BUS	0xFD000000	/* Memory space base addr */
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x01000000	/* Size of Memory window */

#define CONFIG_PCI_IO_BUS	0xFE200000	/* IO space base address */
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x00200000	/* Size of IO window */

#if defined(CONFIG_SH_32BIT)
#define CONFIG_PCI_SYS_PHYS	SH7785LCR_SDRAM_PHYS_BASE
#else
#define CONFIG_PCI_SYS_PHYS	CONFIG_SYS_SDRAM_BASE
#endif
#define CONFIG_PCI_SYS_BUS	CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE	CONFIG_SYS_SDRAM_SIZE

/* ENV setting */
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
/* The SCIF used external clock. system clock only used timer. */
#define CONFIG_SYS_CLK_FREQ	50000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		4

#endif	/* __SH7785LCR_H */
Commit	Line	Data
0d53a47d NI	1	/*
	2	* Configuation settings for the Renesas Technology R0P7785LC0011RL board
	3	*
	4	* Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
0d53a47d NI	7	*/
	8
	9	#ifndef __SH7785LCR_H
	10	#define __SH7785LCR_H
	11
0d53a47d	12	#define CONFIG_CPU_SH7785 1
0d53a47d	13
0d53a47d NI	14	#define CONFIG_EXTRA_ENV_SETTINGS \
	15	"bootdevice=0:1\0" \
	16	"usbload=usb reset;usbboot;usb stop;bootm\0"
	17
18a40e84	18	#define CONFIG_DISPLAY_BOARDINFO
0d53a47d NI	19	#undef CONFIG_SHOW_BOOT_PROGRESS
	20
	21	/* MEMORY */
ada93182	22	#if defined(CONFIG_SH_32BIT)
915d6b7d NI	23	/* 0x40000000 - 0x47FFFFFF does not use */
	24	#define CONFIG_SH_SDRAM_OFFSET (0x8000000)
	25	#define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET)
	26	#define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET)
ada93182 YS	27	#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
	28	#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
	29	#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
	30	#define SH7785LCR_USB_BASE (0xa6000000)
	31	#else
0d53a47d NI	32	#define SH7785LCR_SDRAM_BASE (0x08000000)
	33	#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
	34	#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
	35	#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
	36	#define SH7785LCR_USB_BASE (0xb4000000)
ada93182	37	#endif
0d53a47d	38
6d0f6bcf	39	#define CONFIG_SYS_LONGHELP
6d0f6bcf	40	#define CONFIG_SYS_PBSIZE 256
6d0f6bcf	41	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
0d53a47d NI	42
0d53a47d NI	43	/* SCIF */
0d53a47d NI	44	#define CONFIG_CONS_SCIF1 1
0d53a47d NI	45	#define CONFIG_SCIF_EXT_CLOCK 1
0d53a47d	46
6d0f6bcf JCPV	47	#define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
6d0f6bcf JCPV	48	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
0d53a47d NI	49	(SH7785LCR_SDRAM_SIZE) - \
0d53a47d NI	50	4 * 1024 * 1024)
6d0f6bcf JCPV	51	#undef CONFIG_SYS_ALT_MEMTEST
	52	#undef CONFIG_SYS_MEMTEST_SCRATCH
	53	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
0d53a47d	54
6d0f6bcf JCPV	55	#define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
	56	#define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
	57	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
0d53a47d	58
6d0f6bcf JCPV	59	#define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
	60	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	61	#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
6d0f6bcf	62	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
0d53a47d NI	63
0d53a47d NI	64	/* FLASH */
1c98172e	65	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	66	#define CONFIG_SYS_FLASH_CFI
	67	#undef CONFIG_SYS_FLASH_QUIET_TEST
	68	#define CONFIG_SYS_FLASH_EMPTY_INFO
	69	#define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
	70	#define CONFIG_SYS_MAX_FLASH_SECT 512
	71
	72	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	73	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
0d53a47d NI	74	(0 * SH7785LCR_FLASH_BANK_SIZE) }
0d53a47d NI	75
6d0f6bcf JCPV	76	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
	77	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
	78	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
	79	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
0d53a47d	80
6d0f6bcf JCPV	81	#undef CONFIG_SYS_FLASH_PROTECTION
6d0f6bcf JCPV	82	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
0d53a47d NI	83
0d53a47d NI	84	/* R8A66597 */
0d53a47d NI	85	#define CONFIG_USB_R8A66597_HCD
	86	#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
	87	#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
	88	#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
	89	#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
	90
	91	/* PCI Controller */
0d53a47d NI	92	#define CONFIG_SH4_PCI
0d53a47d NI	93	#define CONFIG_SH7780_PCI
ada93182 YS	94	#if defined(CONFIG_SH_32BIT)
	95	#define CONFIG_SH7780_PCI_LSR 0x1ff00001
	96	#define CONFIG_SH7780_PCI_LAR 0x5f000000
	97	#define CONFIG_SH7780_PCI_BAR 0x5f000000
	98	#else
06b18163 YS	99	#define CONFIG_SH7780_PCI_LSR 0x07f00001
	100	#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
	101	#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
ada93182	102	#endif
0d53a47d NI	103	#define CONFIG_PCI_SCAN_SHOW 1
	104
	105	#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
	106	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	107	#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
	108
	109	#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
	110	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	111	#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
	112
ada93182 YS	113	#if defined(CONFIG_SH_32BIT)
	114	#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
	115	#else
b3061b40	116	#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
ada93182 YS	117	#endif
ada93182 YS	118	#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
b3061b40 YS	119	#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
b3061b40 YS	120
0d53a47d	121	/* ENV setting */
0d53a47d	122	#define CONFIG_ENV_OVERWRITE 1
0e8d1586 JCPV	123	#define CONFIG_ENV_SECT_SIZE (256 * 1024)
0e8d1586 JCPV	124	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	125	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
6d0f6bcf JCPV	126	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586	127	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
0d53a47d NI	128
	129	/* Board Clock */
	130	/* The SCIF used external clock. system clock only used timer. */
	131	#define CONFIG_SYS_CLK_FREQ 50000000
684a501e NI	132	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	133	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	134	#define CONFIG_SYS_TMU_CLK_DIV 4
0d53a47d NI	135
0d53a47d NI	136	#endif /* __SH7785LCR_H */