]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/smdk2410.h
Replace CONFIG_SYS_GBL_DATA_SIZE by auto-generated value
[people/ms/u-boot.git] / include / configs / smdk2410.h
CommitLineData
81a8824f
WD
1/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
792a09eb 5 * Gary Jennejohn <garyj@denx.de>
81a8824f
WD
6 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Configuation settings for the SAMSUNG SMDK2410 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
81a8824f
WD
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
ac67804f 36#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
37#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
38#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
39#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
81a8824f
WD
40
41/* input clock of PLL */
7f6c2cbc 42#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
81a8824f
WD
43
44
45#define USE_920T_MMU 1
46#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
47
48/*
49 * Size of malloc() pool
50 */
6d0f6bcf 51#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
81a8824f
WD
52
53/*
54 * Hardware drivers
55 */
b1c0eaac
BW
56#define CONFIG_NET_MULTI
57#define CONFIG_CS8900 /* we have a CS8900 on-board */
58#define CONFIG_CS8900_BASE 0x19000300
59#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
81a8824f
WD
60
61/*
62 * select serial console configuration
63 */
300f99f4 64#define CONFIG_S3C24X0_SERIAL
81a8824f
WD
65#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
66
48b42616
WD
67/************************************************************
68 * RTC
69 ************************************************************/
70#define CONFIG_RTC_S3C24X0 1
71
81a8824f
WD
72/* allow to overwrite serial and ethaddr */
73#define CONFIG_ENV_OVERWRITE
74
75#define CONFIG_BAUDRATE 115200
76
46da1e96 77
079a136c
JL
78/*
79 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
46da1e96
JL
87/*
88 * Command line configuration.
89 */
90#include <config_cmd_default.h>
91
92#define CONFIG_CMD_CACHE
46da1e96
JL
93#define CONFIG_CMD_DATE
94#define CONFIG_CMD_ELF
95
81a8824f
WD
96
97#define CONFIG_BOOTDELAY 3
53677ef1 98/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
81a8824f
WD
99/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
100#define CONFIG_NETMASK 255.255.255.0
101#define CONFIG_IPADDR 10.0.0.110
102#define CONFIG_SERVERIP 10.0.0.1
103/*#define CONFIG_BOOTFILE "elinos-lart" */
104/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
105
46da1e96 106#if defined(CONFIG_CMD_KGDB)
81a8824f
WD
107#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
108/* what's this ? it's not used anywhere */
109#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
110#endif
111
112/*
113 * Miscellaneous configurable options
114 */
6d0f6bcf
JCPV
115#define CONFIG_SYS_LONGHELP /* undef to save memory */
116#define CONFIG_SYS_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
117#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
118#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
81a8824f 121
6d0f6bcf
JCPV
122#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
123#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
81a8824f 124
6d0f6bcf 125#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
81a8824f 126
cd85662b 127#define CONFIG_SYS_HZ 1000
81a8824f
WD
128
129/* valid baudrates */
6d0f6bcf 130#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
81a8824f
WD
131
132/*-----------------------------------------------------------------------
133 * Stack sizes
134 *
135 * The stack sizes are set up in start.S using the settings below
136 */
137#define CONFIG_STACKSIZE (128*1024) /* regular stack */
138#ifdef CONFIG_USE_IRQ
139#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
140#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
141#endif
142
143/*-----------------------------------------------------------------------
144 * Physical Memory Map
145 */
146#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
147#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
148#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
149
150#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
151
6d0f6bcf 152#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
81a8824f
WD
153
154/*-----------------------------------------------------------------------
155 * FLASH and environment organization
156 */
157
158#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
159#if 0
160#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
161#endif
162
6d0f6bcf 163#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
81a8824f
WD
164#ifdef CONFIG_AMD_LV800
165#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
6d0f6bcf
JCPV
166#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
167#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
81a8824f
WD
168#endif
169#ifdef CONFIG_AMD_LV400
170#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
6d0f6bcf
JCPV
171#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
172#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
81a8824f
WD
173#endif
174
175/* timeout values are in ticks */
6d0f6bcf
JCPV
176#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
177#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
81a8824f 178
5a1aceb0 179#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 180#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
81a8824f
WD
181
182#endif /* __CONFIG_H */