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81a8824f WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
81a8824f WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the SAMSUNG SMDK2410 board. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
81a8824f WD |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
81a8824f WD |
16 | /* |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
f2168440 | 20 | #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ |
d0b375f6 DMEA |
21 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ |
22 | #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ | |
81a8824f | 23 | |
4479fc5b DMEA |
24 | #define CONFIG_SYS_TEXT_BASE 0x0 |
25 | ||
d0b375f6 | 26 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
81a8824f | 27 | |
d0b375f6 DMEA |
28 | /* input clock of PLL (the SMDK2410 has 12MHz input clock) */ |
29 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
81a8824f | 30 | |
d0b375f6 DMEA |
31 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
32 | #define CONFIG_SETUP_MEMORY_TAGS | |
33 | #define CONFIG_INITRD_TAG | |
81a8824f WD |
34 | |
35 | /* | |
36 | * Hardware drivers | |
37 | */ | |
b1c0eaac BW |
38 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
39 | #define CONFIG_CS8900_BASE 0x19000300 | |
40 | #define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ | |
81a8824f WD |
41 | |
42 | /* | |
43 | * select serial console configuration | |
44 | */ | |
300f99f4 | 45 | #define CONFIG_S3C24X0_SERIAL |
d0b375f6 DMEA |
46 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ |
47 | ||
48 | /************************************************************ | |
49 | * USB support (currently only works with D-cache off) | |
50 | ************************************************************/ | |
51 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 52 | #define CONFIG_USB_OHCI_S3C24XX |
d0b375f6 DMEA |
53 | #define CONFIG_USB_KEYBOARD |
54 | #define CONFIG_USB_STORAGE | |
55 | #define CONFIG_DOS_PARTITION | |
81a8824f | 56 | |
48b42616 WD |
57 | /************************************************************ |
58 | * RTC | |
59 | ************************************************************/ | |
d0b375f6 | 60 | #define CONFIG_RTC_S3C24X0 |
48b42616 | 61 | |
81a8824f WD |
62 | #define CONFIG_BAUDRATE 115200 |
63 | ||
079a136c JL |
64 | /* |
65 | * BOOTP options | |
66 | */ | |
67 | #define CONFIG_BOOTP_BOOTFILESIZE | |
68 | #define CONFIG_BOOTP_BOOTPATH | |
69 | #define CONFIG_BOOTP_GATEWAY | |
70 | #define CONFIG_BOOTP_HOSTNAME | |
71 | ||
46da1e96 JL |
72 | /* |
73 | * Command line configuration. | |
74 | */ | |
d0b375f6 | 75 | #define CONFIG_CMD_BSP |
46da1e96 | 76 | #define CONFIG_CMD_DATE |
d0b375f6 | 77 | #define CONFIG_CMD_NAND |
d0b375f6 | 78 | #define CONFIG_CMD_REGINFO |
d0b375f6 | 79 | |
d0b375f6 DMEA |
80 | #define CONFIG_CMDLINE_EDITING |
81 | ||
82 | /* autoboot */ | |
d0b375f6 DMEA |
83 | #define CONFIG_BOOT_RETRY_TIME -1 |
84 | #define CONFIG_RESET_TO_RETRY | |
85 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
86 | ||
87 | #define CONFIG_NETMASK 255.255.255.0 | |
81a8824f WD |
88 | #define CONFIG_IPADDR 10.0.0.110 |
89 | #define CONFIG_SERVERIP 10.0.0.1 | |
81a8824f | 90 | |
46da1e96 | 91 | #if defined(CONFIG_CMD_KGDB) |
d0b375f6 | 92 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
81a8824f WD |
93 | #endif |
94 | ||
95 | /* | |
96 | * Miscellaneous configurable options | |
97 | */ | |
d0b375f6 | 98 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
d0b375f6 DMEA |
99 | #define CONFIG_SYS_CBSIZE 256 |
100 | /* Print Buffer Size */ | |
101 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
102 | sizeof(CONFIG_SYS_PROMPT)+16) | |
103 | #define CONFIG_SYS_MAXARGS 16 | |
104 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
105 | ||
3d3206f1 | 106 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
81a8824f | 107 | |
d0b375f6 DMEA |
108 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
109 | #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ | |
81a8824f | 110 | |
d0b375f6 | 111 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
81a8824f | 112 | |
d0b375f6 DMEA |
113 | /* support additional compression methods */ |
114 | #define CONFIG_BZIP2 | |
115 | #define CONFIG_LZO | |
116 | #define CONFIG_LZMA | |
117 | ||
81a8824f WD |
118 | /*----------------------------------------------------------------------- |
119 | * Physical Memory Map | |
120 | */ | |
d0b375f6 | 121 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
81a8824f WD |
122 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ |
123 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
124 | ||
d0b375f6 | 125 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */ |
81a8824f | 126 | |
a5ec7f64 | 127 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
81a8824f WD |
128 | |
129 | /*----------------------------------------------------------------------- | |
130 | * FLASH and environment organization | |
131 | */ | |
132 | ||
a5ec7f64 DMEA |
133 | #define CONFIG_SYS_FLASH_CFI |
134 | #define CONFIG_FLASH_CFI_DRIVER | |
135 | #define CONFIG_FLASH_CFI_LEGACY | |
136 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
137 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
81a8824f | 138 | |
a5ec7f64 | 139 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
d0b375f6 | 140 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
a5ec7f64 | 141 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
81a8824f | 142 | |
d0b375f6 DMEA |
143 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) |
144 | #define CONFIG_ENV_IS_IN_FLASH | |
145 | #define CONFIG_ENV_SIZE 0x10000 | |
146 | /* allow to overwrite serial and ethaddr */ | |
147 | #define CONFIG_ENV_OVERWRITE | |
148 | ||
149 | /* | |
150 | * Size of malloc() pool | |
151 | * BZIP2 / LZO / LZMA need a lot of RAM | |
152 | */ | |
153 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
81a8824f | 154 | |
a5ec7f64 DMEA |
155 | #define CONFIG_SYS_MONITOR_LEN (448 * 1024) |
156 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
157 | ||
d0b375f6 DMEA |
158 | /* |
159 | * NAND configuration | |
160 | */ | |
161 | #ifdef CONFIG_CMD_NAND | |
162 | #define CONFIG_NAND_S3C2410 | |
163 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
164 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
d0b375f6 DMEA |
165 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
166 | #endif | |
167 | ||
168 | /* | |
169 | * File system | |
170 | */ | |
d0b375f6 DMEA |
171 | #define CONFIG_CMD_UBI |
172 | #define CONFIG_CMD_UBIFS | |
173 | #define CONFIG_CMD_MTDPARTS | |
174 | #define CONFIG_MTD_DEVICE | |
175 | #define CONFIG_MTD_PARTITIONS | |
176 | #define CONFIG_YAFFS2 | |
177 | #define CONFIG_RBTREE | |
178 | ||
b9f15902 DMEA |
179 | /* additions for new relocation code, must be added to all boards */ |
180 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
181 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
182 | GENERATED_GBL_DATA_SIZE) | |
183 | ||
d0b375f6 | 184 | #define CONFIG_BOARD_EARLY_INIT_F |
b9f15902 | 185 | |
d0b375f6 | 186 | #endif /* __CONFIG_H */ |