[people/ms/u-boot.git] / include / configs / smdk5250.h

/*
 * Copyright (C) 2011 Samsung Electronics
 *
 * Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
#define CONFIG_S5P			/* S5P Family */
#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
#define CONFIG_SMDK5250			/* which is in a SMDK5250 */

#include <asm/arch/cpu.h>		/* get chip and board defs */

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Keep L2 Cache Disabled */
#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_TEXT_BASE		0x43E00000

/* input clock of PLL: SMDK5250 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ		24000000

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING

/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
#define MACH_TYPE_SMDK5250		3774
#define CONFIG_MACH_TYPE		MACH_TYPE_SMDK5250

/* Power Down Modes */
#define S5P_CHECK_SLEEP			0x00000BAD
#define S5P_CHECK_DIDLE			0xBAD00000
#define S5P_CHECK_LPA			0xABAD0000

/* Offset for inform registers */
#define INFORM0_OFFSET			0x800
#define INFORM1_OFFSET			0x804

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))

/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL1			/* use SERIAL 1 */
#define CONFIG_BAUDRATE			115200
#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000

#define TZPC_BASE_OFFSET		0x10000

/* SD/MMC configuration */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_SDHCI
#define CONFIG_S5P_SDHCI

#define CONFIG_BOARD_EARLY_INIT_F

/* PWM */
#define CONFIG_PWM

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* Command definition*/
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MMC
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_NET

#define CONFIG_BOOTDELAY		3
#define CONFIG_ZERO_BOOTDELAY_CHECK

/* MMC SPL */
#define CONFIG_SPL
#define COPY_BL2_FNPTR_ADDR	0x02020030

#define CONFIG_BOOTCOMMAND	"mmc read 40007000 451 2000; bootm 40007000"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
#define CONFIG_SYS_PROMPT		"SMDK5250 # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC1,115200n8\0"
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)

#define CONFIG_SYS_HZ			1000

#define CONFIG_RD_LVL

/* Stack sizes */
#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */

#define CONFIG_NR_DRAM_BANKS	8
#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_5		(CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_5_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_6		(CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_6_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_7		(CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_7_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_8		(CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_8_SIZE	SDRAM_BANK_SIZE

#define CONFIG_SYS_MONITOR_BASE	0x00000000

/* FLASH and environment organization */
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_IMLS
#define CONFIG_IDENT_STRING		" for SMDK5250"

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0

#define CONFIG_SECURE_BL1_ONLY

/* Secure FW size configuration */
#ifdef	CONFIG_SECURE_BL1_ONLY
#define	CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
#else
#define	CONFIG_SEC_FW_SIZE		0
#endif

/* Configuration of BL1, BL2, ENV Blocks on mmc */
#define CONFIG_RES_BLOCK_SIZE	(512)
#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
#define	CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */

#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)

/* U-boot copy size from boot Media to DRAM.*/
#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
#define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
#define CONFIG_DOS_PARTITION

#define CONFIG_IRAM_STACK	0x02050000

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - 0x1000000)

/* Ethernet Controllor Driver */
#ifdef CONFIG_CMD_NET
#define CONFIG_SMC911X
#define CONFIG_SMC911X_BASE		0x5000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_ENV_SROM_BANK		1
#endif /*CONFIG_CMD_NET*/

/* Enable devicetree support */
#define CONFIG_OF_LIBFDT

#endif	/* __CONFIG_H */
Commit	Line	Data
0aee53ba CK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	*
	4	* Configuration settings for the SAMSUNG SMDK5250 (EXYNOS5250) board.
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/* High Level Configuration Options */
	29	#define CONFIG_SAMSUNG /* in a SAMSUNG core */
	30	#define CONFIG_S5P /* S5P Family */
	31	#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
	32	#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
	33
	34	#include <asm/arch/cpu.h> /* get chip and board defs */
	35
	36	#define CONFIG_ARCH_CPU_INIT
	37	#define CONFIG_DISPLAY_CPUINFO
	38	#define CONFIG_DISPLAY_BOARDINFO
	39
	40	/* Keep L2 Cache Disabled */
	41	#define CONFIG_SYS_DCACHE_OFF
	42
	43	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	44	#define CONFIG_SYS_TEXT_BASE 0x43E00000
	45
	46	/* input clock of PLL: SMDK5250 has 24MHz input clock */
	47	#define CONFIG_SYS_CLK_FREQ 24000000
	48
	49	#define CONFIG_SETUP_MEMORY_TAGS
	50	#define CONFIG_CMDLINE_TAG
	51	#define CONFIG_INITRD_TAG
	52	#define CONFIG_CMDLINE_EDITING
	53
	54	/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
	55	#define MACH_TYPE_SMDK5250 3774
	56	#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
	57
	58	/* Power Down Modes */
	59	#define S5P_CHECK_SLEEP 0x00000BAD
	60	#define S5P_CHECK_DIDLE 0xBAD00000
	61	#define S5P_CHECK_LPA 0xABAD0000
	62
	63	/* Offset for inform registers */
	64	#define INFORM0_OFFSET 0x800
65	#define INFORM1_OFFSET 0x804
66
67	/* Size of malloc() pool */
68	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
69
70	/* select serial console configuration */
71	#define CONFIG_SERIAL_MULTI
72	#define CONFIG_SERIAL1 /* use SERIAL 1 */
73	#define CONFIG_BAUDRATE 115200
74	#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
75
76	#define TZPC_BASE_OFFSET 0x10000
77
78	/* SD/MMC configuration */
79	#define CONFIG_GENERIC_MMC
80	#define CONFIG_MMC
7d2d58b4 JC	81	#define CONFIG_SDHCI
7d2d58b4 JC	82	#define CONFIG_S5P_SDHCI
0aee53ba CK	83
	84	#define CONFIG_BOARD_EARLY_INIT_F
	85
	86	/* PWM */
	87	#define CONFIG_PWM
	88
	89	/* allow to overwrite serial and ethaddr */
	90	#define CONFIG_ENV_OVERWRITE
	91
	92	/* Command definition*/
	93	#include <config_cmd_default.h>
	94
	95	#define CONFIG_CMD_PING
	96	#define CONFIG_CMD_ELF
	97	#define CONFIG_CMD_MMC
	98	#define CONFIG_CMD_EXT2
	99	#define CONFIG_CMD_FAT
bf936210	100	#define CONFIG_CMD_NET
0aee53ba CK	101
	102	#define CONFIG_BOOTDELAY 3
	103	#define CONFIG_ZERO_BOOTDELAY_CHECK
	104
81e35203 CK	105	/* MMC SPL */
	106	#define CONFIG_SPL
	107	#define COPY_BL2_FNPTR_ADDR 0x02020030
	108
0aee53ba CK	109	#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
	110
	111	/* Miscellaneous configurable options */
	112	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	113	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
0aee53ba CK	114	#define CONFIG_SYS_PROMPT "SMDK5250 # "
	115	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	116	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	117	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	118	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
	119	/* Boot Argument Buffer Size */
	120	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	121	/* memtest works on */
	122	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	123	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
	124	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
	125
	126	#define CONFIG_SYS_HZ 1000
	127
0aee53ba CK	128	#define CONFIG_RD_LVL
	129
	130	/* Stack sizes */
	131	#define CONFIG_STACKSIZE (256 << 10) /* 256KB */
	132
	133	#define CONFIG_NR_DRAM_BANKS 8
	134	#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
	135	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	136	#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
	137	#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
	138	#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
	139	#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
	140	#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
	141	#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
	142	#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
	143	#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
	144	#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
	145	#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
	146	#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
	147	#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
	148	#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
	149	#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
	150	#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
	151
	152	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	153
	154	/* FLASH and environment organization */
	155	#define CONFIG_SYS_NO_FLASH
	156	#undef CONFIG_CMD_IMLS
	157	#define CONFIG_IDENT_STRING " for SMDK5250"
	158
	159	#define CONFIG_ENV_IS_IN_MMC
	160	#define CONFIG_SYS_MMC_ENV_DEV 0
	161
	162	#define CONFIG_SECURE_BL1_ONLY
	163
	164	/* Secure FW size configuration */
	165	#ifdef CONFIG_SECURE_BL1_ONLY
	166	#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
	167	#else
	168	#define CONFIG_SEC_FW_SIZE 0
	169	#endif
	170
	171	/* Configuration of BL1, BL2, ENV Blocks on mmc */
	172	#define CONFIG_RES_BLOCK_SIZE (512)
	173	#define CONFIG_BL1_SIZE (16 << 10) /16 K reserved for BL1/
	174	#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
	175	#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
	176
	177	#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
	178	#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
	179	#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
	180
81e35203 CK	181	/* U-boot copy size from boot Media to DRAM.*/
	182	#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
	183	#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
0aee53ba CK	184	#define CONFIG_DOS_PARTITION
	185
	186	#define CONFIG_IRAM_STACK 0x02050000
	187
	188	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000)
	189
bf936210 CK	190	/* Ethernet Controllor Driver */
	191	#ifdef CONFIG_CMD_NET
	192	#define CONFIG_SMC911X
	193	#define CONFIG_SMC911X_BASE 0x5000000
	194	#define CONFIG_SMC911X_16_BIT
	195	#define CONFIG_ENV_SROM_BANK 1
	196	#endif /CONFIG_CMD_NET/
	197
0aee53ba CK	198	/* Enable devicetree support */
	199	#define CONFIG_OF_LIBFDT
	200
	201	#endif /* __CONFIG_H */