[people/ms/u-boot.git] / include / configs / smdk6400.h

/*
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Marius Groeger <mgroeger@sysgo.de>
 * Gary Jennejohn <garyj@denx.de>
 * David Mueller <d.mueller@elsoft.ch>
 *
 * (C) Copyright 2008
 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
 *
 * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_S3C6400		1	/* in a SAMSUNG S3C6400 SoC     */
#define CONFIG_S3C64XX		1	/* in a SAMSUNG S3C64XX Family  */
#define CONFIG_SMDK6400		1	/* on a SAMSUNG SMDK6400 Board  */

#define CONFIG_SKIP_RELOCATE_UBOOT

#define CONFIG_PERIPORT_REMAP
#define CONFIG_PERIPORT_BASE	0x70000000
#define CONFIG_PERIPORT_SIZE	0x13

#define CONFIG_SYS_SDRAM_BASE	0x50000000

/* input clock of PLL: SMDK6400 has 12MHz input clock */
#define CONFIG_SYS_CLK_FREQ	12000000

#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
#define CONFIG_ENABLE_MMU
#endif

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG

/*
 * Architecture magic and machine type
 */
#define MACH_TYPE		1270

#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for initial data */

/*
 * Hardware drivers
 */
#define CONFIG_NET_MULTI
#define CONFIG_CS8900			/* we have a CS8900 on-board	*/
#define CONFIG_CS8900_BASE	  	0x18800300
#define CONFIG_CS8900_BUS16		/* follow the Linux driver	*/

/*
 * select serial console configuration
 */
#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK6400	*/

#define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
#ifdef CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#endif

#define CONFIG_CMDLINE_EDITING

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_BAUDRATE		115200

/***********************************************************
 * Command definition
 ***********************************************************/
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_NAND
#if defined(CONFIG_BOOT_ONENAND)
#define CONFIG_CMD_ONENAND
#endif
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2

#define CONFIG_BOOTDELAY	3

#define CONFIG_ZERO_BOOTDELAY_CHECK

#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	115200	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	1	/* which serial port to use	 */
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory	      */
#define CONFIG_SYS_PROMPT		"SMDK6400 # "	/* Monitor Command Prompt     */
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size    */
#define CONFIG_SYS_PBSIZE		384		/* Print Buffer Size          */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size  */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* memtest works on	      */
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */

#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* default load address	*/

#define CONFIG_SYS_HZ			1000

/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKSIZE	0x40000		/* regular stack 256KB */

/**********************************
 Support Clock Settings
 **********************************
 Setting	SYNC	ASYNC
 ----------------------------------
 667_133_66	 X	  O
 533_133_66	 O	  O
 400_133_66	 X	  O
 400_100_50	 O	  O
 **********************************/

/*#define CONFIG_CLK_667_133_66*/
#define CONFIG_CLK_533_133_66
/*
#define CONFIG_CLK_400_100_50
#define CONFIG_CLK_400_133_66
#define CONFIG_SYNC_MODE
*/

/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1	*/
#define PHYS_SDRAM_1_SIZE	0x08000000	/* 128 MB in Bank #1	*/

#define CONFIG_SYS_FLASH_BASE		0x10000000
#define CONFIG_SYS_MONITOR_BASE	0x00000000

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/
/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
#define CONFIG_SYS_MAX_FLASH_SECT	40

#define CONFIG_AMD_LV800
#define CONFIG_SYS_FLASH_CFI		1	/* Use CFI parameters (needed?) */
/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant	*/
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16

/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	(5 * CONFIG_SYS_HZ) /* Timeout for Flash Write	*/

#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector */

/*
 * SMDK6400 board specific data
 */

#define CONFIG_IDENT_STRING	" for SMDK6400"

/* base address for uboot */
#define CONFIG_SYS_PHY_UBOOT_BASE	(CONFIG_SYS_SDRAM_BASE + 0x07e00000)
/* total memory available to uboot */
#define CONFIG_SYS_UBOOT_SIZE		(1024 * 1024)

/* Put environment copies after the end of U-Boot owned RAM */
#define CONFIG_NAND_ENV_DST	(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)

#ifdef CONFIG_ENABLE_MMU
#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
#define CONFIG_BOOTCOMMAND	"nand read 0xc0018000 0x60000 0x1c0000;" \
				"bootm 0xc0018000"
#else
#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
#define CONFIG_BOOTCOMMAND	"nand read 0x50018000 0x60000 0x1c0000;" \
				"bootm 0x50018000"
#endif

/* NAND U-Boot load and start address */
#define CONFIG_SYS_UBOOT_BASE		(CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)

#define CONFIG_ENV_OFFSET		0x0040000

/* NAND configuration */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		0x70200010
#define CONFIG_SYS_S3C_NAND_HWECC

#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I	1  /* ".i" read skips bad blocks	      */
#define CONFIG_SYS_NAND_WP		1
#define CONFIG_SYS_NAND_YAFFS_WRITE	1  /* support yaffs write		      */
#define CONFIG_SYS_NAND_BBT_2NDPAGE	1  /* bad-block markers in 1st and 2nd pages  */

#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_PHY_UBOOT_BASE	/* NUB load-addr      */
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST	/* NUB start-addr     */

#define CONFIG_SYS_NAND_U_BOOT_OFFS	(4 * 1024)	/* Offset to RAM U-Boot image */
#define CONFIG_SYS_NAND_U_BOOT_SIZE	(252 * 1024)	/* Size of RAM U-Boot image   */

/* NAND chip page size		*/
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
/* NAND chip block size		*/
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
/* NAND chip page per block count  */
#define CONFIG_SYS_NAND_PAGE_COUNT	64
/* Location of the bad-block label */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
/* Extra address cycle for > 128MiB */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
#define CONFIG_SYS_NAND_ECCSIZE	CONFIG_SYS_NAND_PAGE_SIZE
/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
#define CONFIG_SYS_NAND_ECCBYTES	4
/* Number of ECC-blocks per NAND page */
#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
/* Size of a single OOB region */
#define CONFIG_SYS_NAND_OOBSIZE	64
/* Number of ECC bytes per page */
#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
/* ECC byte positions */
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
				 48, 49, 50, 51, 52, 53, 54, 55, \
				 56, 57, 58, 59, 60, 61, 62, 63}

/* Boot configuration (define only one of next 3) */
#define CONFIG_BOOT_NAND
/* None of these are currently implemented. Left from the original Samsung
 * version for reference
#define CONFIG_BOOT_NOR
#define CONFIG_BOOT_MOVINAND
#define CONFIG_BOOT_ONENAND
*/

#define CONFIG_NAND
#define CONFIG_NAND_S3C64XX
/* Unimplemented or unsupported. See comment above.
#define CONFIG_ONENAND
#define CONFIG_MOVINAND
*/

/* Settings as above boot configuration */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_BOOTARGS		"console=ttySAC,115200"

#if !defined(CONFIG_ENABLE_MMU)
#define CONFIG_CMD_USB			1
#define CONFIG_USB_S3C64XX
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x74300000
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"s3c6400"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1

#define CONFIG_USB_STORAGE	1
#endif
#define CONFIG_DOS_PARTITION	1

#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
# error "usb_ohci.c is currently broken with MMU enabled."
#endif

#endif	/* __CONFIG_H */
Commit	Line	Data
11edcfe2 GL	1	/*
	2	* (C) Copyright 2002
	3	* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
	4	* Marius Groeger <mgroeger@sysgo.de>
792a09eb	5	* Gary Jennejohn <garyj@denx.de>
11edcfe2 GL	6	* David Mueller <d.mueller@elsoft.ch>
	7	*
	8	* (C) Copyright 2008
	9	* Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
	10	*
	11	* Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
	12	*
	13	* See file CREDITS for list of people who contributed to this
	14	* project.
	15	*
	16	* This program is free software; you can redistribute it and/or
	17	* modify it under the terms of the GNU General Public License as
	18	* published by the Free Software Foundation; either version 2 of
	19	* the License, or (at your option) any later version.
	20	*
	21	* This program is distributed in the hope that it will be useful,
	22	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	24	* GNU General Public License for more details.
	25	*
	26	* You should have received a copy of the GNU General Public License
	27	* along with this program; if not, write to the Free Software
	28	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	29	* MA 02111-1307 USA
	30	*/
	31
	32	#ifndef __CONFIG_H
	33	#define __CONFIG_H
	34
	35	/*
	36	* High Level Configuration Options
	37	* (easy to change)
	38	*/
	39	#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
	40	#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
	41	#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
	42
678e008c CC	43	#define CONFIG_SKIP_RELOCATE_UBOOT
	44
	45	#define CONFIG_PERIPORT_REMAP
	46	#define CONFIG_PERIPORT_BASE 0x70000000
	47	#define CONFIG_PERIPORT_SIZE 0x13
	48
6d0f6bcf	49	#define CONFIG_SYS_SDRAM_BASE 0x50000000
11edcfe2 GL	50
	51	/* input clock of PLL: SMDK6400 has 12MHz input clock */
	52	#define CONFIG_SYS_CLK_FREQ 12000000
	53
14d0a02a	54	#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000)
11edcfe2 GL	55	#define CONFIG_ENABLE_MMU
	56	#endif
	57
11edcfe2 GL	58	#define CONFIG_SETUP_MEMORY_TAGS
	59	#define CONFIG_CMDLINE_TAG
	60	#define CONFIG_INITRD_TAG
	61
	62	/*
	63	* Architecture magic and machine type
	64	*/
	65	#define MACH_TYPE 1270
	66
	67	#define CONFIG_DISPLAY_CPUINFO
	68	#define CONFIG_DISPLAY_BOARDINFO
	69
11edcfe2 GL	70	/*
	71	* Size of malloc() pool
	72	*/
6d0f6bcf JCPV	73	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
6d0f6bcf JCPV	74	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
11edcfe2 GL	75
	76	/*
	77	* Hardware drivers
	78	*/
b1c0eaac BW	79	#define CONFIG_NET_MULTI
	80	#define CONFIG_CS8900 /* we have a CS8900 on-board */
	81	#define CONFIG_CS8900_BASE 0x18800300
	82	#define CONFIG_CS8900_BUS16 /* follow the Linux driver */
11edcfe2 GL	83
	84	/*
	85	* select serial console configuration
	86	*/
	87	#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
	88
6d0f6bcf JCPV	89	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	90	#ifdef CONFIG_SYS_HUSH_PARSER
	91	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
11edcfe2 GL	92	#endif
	93
	94	#define CONFIG_CMDLINE_EDITING
	95
	96	/* allow to overwrite serial and ethaddr */
	97	#define CONFIG_ENV_OVERWRITE
	98
	99	#define CONFIG_BAUDRATE 115200
	100
	101	/***********************************************************
	102	* Command definition
	103	***********************************************************/
	104	#include <config_cmd_default.h>
	105
	106	#define CONFIG_CMD_CACHE
	107	#define CONFIG_CMD_REGINFO
	108	#define CONFIG_CMD_LOADS
	109	#define CONFIG_CMD_LOADB
bdab39d3	110	#define CONFIG_CMD_SAVEENV
11edcfe2 GL	111	#define CONFIG_CMD_NAND
	112	#if defined(CONFIG_BOOT_ONENAND)
	113	#define CONFIG_CMD_ONENAND
	114	#endif
	115	#define CONFIG_CMD_PING
	116	#define CONFIG_CMD_ELF
	117	#define CONFIG_CMD_FAT
	118	#define CONFIG_CMD_EXT2
	119
	120	#define CONFIG_BOOTDELAY 3
	121
	122	#define CONFIG_ZERO_BOOTDELAY_CHECK
	123
	124	#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
	125	#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
	126	#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
	127	#endif
	128
	129	/*
	130	* Miscellaneous configurable options
	131	*/
6d0f6bcf JCPV	132	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	133	#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
	134	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	135	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	136	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	137	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
11edcfe2	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
6d0f6bcf JCPV	140	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
11edcfe2	141
6d0f6bcf	142	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
11edcfe2	143
6d0f6bcf	144	#define CONFIG_SYS_HZ 1000
11edcfe2 GL	145
11edcfe2 GL	146	/* valid baudrates */
6d0f6bcf	147	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
11edcfe2 GL	148
	149	/*-----------------------------------------------------------------------
	150	* Stack sizes
	151	*
	152	* The stack sizes are set up in start.S using the settings below
	153	*/
	154	#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
	155
	156	/**********************************
	157	Support Clock Settings
	158	**********************************
	159	Setting SYNC ASYNC
	160	----------------------------------
	161	667_133_66 X O
	162	533_133_66 O O
	163	400_133_66 X O
	164	400_100_50 O O
	165	**********************************/
	166
	167	/#define CONFIG_CLK_667_133_66/
	168	#define CONFIG_CLK_533_133_66
	169	/*
	170	#define CONFIG_CLK_400_100_50
	171	#define CONFIG_CLK_400_133_66
	172	#define CONFIG_SYNC_MODE
	173	*/
	174
	175	/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
	176	#define CONFIG_NR_DRAM_BANKS 1
6d0f6bcf	177	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
11edcfe2 GL	178	#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
11edcfe2 GL	179
6d0f6bcf JCPV	180	#define CONFIG_SYS_FLASH_BASE 0x10000000
6d0f6bcf JCPV	181	#define CONFIG_SYS_MONITOR_BASE 0x00000000
11edcfe2 GL	182
	183	/*-----------------------------------------------------------------------
	184	* FLASH and environment organization
	185	*/
6d0f6bcf	186	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
11edcfe2	187	/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
6d0f6bcf	188	#define CONFIG_SYS_MAX_FLASH_SECT 40
11edcfe2 GL	189
11edcfe2 GL	190	#define CONFIG_AMD_LV800
6d0f6bcf	191	#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */
11edcfe2	192	/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
f9f692e2	193	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	194	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
11edcfe2	195	#define CONFIG_FLASH_CFI_LEGACY
6d0f6bcf	196	#define CONFIG_SYS_FLASH_LEGACY_512Kx16
11edcfe2 GL	197
11edcfe2 GL	198	/* timeout values are in ticks */
6d0f6bcf JCPV	199	#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
6d0f6bcf JCPV	200	#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
11edcfe2	201
0e8d1586	202	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
11edcfe2 GL	203
	204	/*
	205	* SMDK6400 board specific data
	206	*/
	207
	208	#define CONFIG_IDENT_STRING " for SMDK6400"
	209
	210	/* base address for uboot */
6d0f6bcf	211	#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000)
11edcfe2	212	/* total memory available to uboot */
6d0f6bcf	213	#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
11edcfe2	214
b74ab737 GL	215	/* Put environment copies after the end of U-Boot owned RAM */
	216	#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
	217
11edcfe2	218	#ifdef CONFIG_ENABLE_MMU
6d0f6bcf	219	#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
11edcfe2 GL	220	#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
	221	"bootm 0xc0018000"
	222	#else
6d0f6bcf	223	#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
11edcfe2 GL	224	#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
	225	"bootm 0x50018000"
	226	#endif
	227
	228	/* NAND U-Boot load and start address */
6d0f6bcf	229	#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
11edcfe2	230
0e8d1586	231	#define CONFIG_ENV_OFFSET 0x0040000
11edcfe2 GL	232
11edcfe2 GL	233	/* NAND configuration */
6d0f6bcf JCPV	234	#define CONFIG_SYS_MAX_NAND_DEVICE 1
6d0f6bcf JCPV	235	#define CONFIG_SYS_NAND_BASE 0x70200010
6d0f6bcf	236	#define CONFIG_SYS_S3C_NAND_HWECC
11edcfe2	237
6d0f6bcf JCPV	238	#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
	239	#define CONFIG_SYS_NAND_WP 1
	240	#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
	241	#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
11edcfe2	242
6d0f6bcf JCPV	243	#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
6d0f6bcf JCPV	244	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
11edcfe2	245
6d0f6bcf JCPV	246	#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
6d0f6bcf JCPV	247	#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
11edcfe2 GL	248
11edcfe2 GL	249	/* NAND chip page size */
6d0f6bcf	250	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
11edcfe2	251	/* NAND chip block size */
6d0f6bcf	252	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
11edcfe2	253	/* NAND chip page per block count */
6d0f6bcf	254	#define CONFIG_SYS_NAND_PAGE_COUNT 64
11edcfe2	255	/* Location of the bad-block label */
6d0f6bcf	256	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
11edcfe2	257	/* Extra address cycle for > 128MiB */
6d0f6bcf	258	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
11edcfe2 GL	259
11edcfe2 GL	260	/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
6d0f6bcf	261	#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
11edcfe2	262	/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
6d0f6bcf	263	#define CONFIG_SYS_NAND_ECCBYTES 4
11edcfe2	264	/* Number of ECC-blocks per NAND page */
6d0f6bcf	265	#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
11edcfe2	266	/* Size of a single OOB region */
6d0f6bcf	267	#define CONFIG_SYS_NAND_OOBSIZE 64
11edcfe2	268	/* Number of ECC bytes per page */
6d0f6bcf	269	#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
11edcfe2	270	/* ECC byte positions */
6d0f6bcf	271	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
11edcfe2 GL	272	48, 49, 50, 51, 52, 53, 54, 55, \
	273	56, 57, 58, 59, 60, 61, 62, 63}
	274
	275	/* Boot configuration (define only one of next 3) */
	276	#define CONFIG_BOOT_NAND
	277	/* None of these are currently implemented. Left from the original Samsung
	278	* version for reference
	279	#define CONFIG_BOOT_NOR
	280	#define CONFIG_BOOT_MOVINAND
	281	#define CONFIG_BOOT_ONENAND
	282	*/
	283
	284	#define CONFIG_NAND
	285	#define CONFIG_NAND_S3C64XX
	286	/* Unimplemented or unsupported. See comment above.
	287	#define CONFIG_ONENAND
	288	#define CONFIG_MOVINAND
	289	*/
	290
	291	/* Settings as above boot configuration */
51bfee19	292	#define CONFIG_ENV_IS_IN_NAND
11edcfe2	293	#define CONFIG_BOOTARGS "console=ttySAC,115200"
11edcfe2 GL	294
	295	#if !defined(CONFIG_ENABLE_MMU)
	296	#define CONFIG_CMD_USB 1
6d27bca1	297	#define CONFIG_USB_S3C64XX
11edcfe2	298	#define CONFIG_USB_OHCI_NEW 1
6d0f6bcf JCPV	299	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
	300	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400"
	301	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
	302	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
11edcfe2 GL	303
	304	#define CONFIG_USB_STORAGE 1
	305	#endif
	306	#define CONFIG_DOS_PARTITION 1
	307
	308	#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
	309	# error "usb_ohci.c is currently broken with MMU enabled."
	310	#endif
	311
	312	#endif /* __CONFIG_H */