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11edcfe2 GL |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
11edcfe2 GL |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * (C) Copyright 2008 | |
9 | * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> | |
10 | * | |
11 | * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board. | |
12 | * | |
13 | * See file CREDITS for list of people who contributed to this | |
14 | * project. | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or | |
17 | * modify it under the terms of the GNU General Public License as | |
18 | * published by the Free Software Foundation; either version 2 of | |
19 | * the License, or (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
29 | * MA 02111-1307 USA | |
30 | */ | |
31 | ||
32 | #ifndef __CONFIG_H | |
33 | #define __CONFIG_H | |
34 | ||
35 | /* | |
36 | * High Level Configuration Options | |
37 | * (easy to change) | |
38 | */ | |
39 | #define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */ | |
40 | #define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ | |
41 | #define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */ | |
42 | ||
6d0f6bcf | 43 | #define CONFIG_SYS_SDRAM_BASE 0x50000000 |
11edcfe2 GL |
44 | |
45 | /* input clock of PLL: SMDK6400 has 12MHz input clock */ | |
46 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
47 | ||
48 | #if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000) | |
49 | #define CONFIG_ENABLE_MMU | |
50 | #endif | |
51 | ||
11edcfe2 GL |
52 | #define CONFIG_SETUP_MEMORY_TAGS |
53 | #define CONFIG_CMDLINE_TAG | |
54 | #define CONFIG_INITRD_TAG | |
55 | ||
56 | /* | |
57 | * Architecture magic and machine type | |
58 | */ | |
59 | #define MACH_TYPE 1270 | |
60 | ||
61 | #define CONFIG_DISPLAY_CPUINFO | |
62 | #define CONFIG_DISPLAY_BOARDINFO | |
63 | ||
64 | #undef CONFIG_SKIP_RELOCATE_UBOOT | |
65 | ||
66 | /* | |
67 | * Size of malloc() pool | |
68 | */ | |
6d0f6bcf JCPV |
69 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) |
70 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */ | |
11edcfe2 GL |
71 | |
72 | /* | |
73 | * Hardware drivers | |
74 | */ | |
b1c0eaac BW |
75 | #define CONFIG_NET_MULTI |
76 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ | |
77 | #define CONFIG_CS8900_BASE 0x18800300 | |
78 | #define CONFIG_CS8900_BUS16 /* follow the Linux driver */ | |
11edcfe2 GL |
79 | |
80 | /* | |
81 | * select serial console configuration | |
82 | */ | |
83 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */ | |
84 | ||
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
86 | #ifdef CONFIG_SYS_HUSH_PARSER | |
87 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
11edcfe2 GL |
88 | #endif |
89 | ||
90 | #define CONFIG_CMDLINE_EDITING | |
91 | ||
92 | /* allow to overwrite serial and ethaddr */ | |
93 | #define CONFIG_ENV_OVERWRITE | |
94 | ||
95 | #define CONFIG_BAUDRATE 115200 | |
96 | ||
97 | /*********************************************************** | |
98 | * Command definition | |
99 | ***********************************************************/ | |
100 | #include <config_cmd_default.h> | |
101 | ||
102 | #define CONFIG_CMD_CACHE | |
103 | #define CONFIG_CMD_REGINFO | |
104 | #define CONFIG_CMD_LOADS | |
105 | #define CONFIG_CMD_LOADB | |
bdab39d3 | 106 | #define CONFIG_CMD_SAVEENV |
11edcfe2 GL |
107 | #define CONFIG_CMD_NAND |
108 | #if defined(CONFIG_BOOT_ONENAND) | |
109 | #define CONFIG_CMD_ONENAND | |
110 | #endif | |
111 | #define CONFIG_CMD_PING | |
112 | #define CONFIG_CMD_ELF | |
113 | #define CONFIG_CMD_FAT | |
114 | #define CONFIG_CMD_EXT2 | |
115 | ||
116 | #define CONFIG_BOOTDELAY 3 | |
117 | ||
118 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
119 | ||
120 | #if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) | |
121 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ | |
122 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
123 | #endif | |
124 | ||
125 | /* | |
126 | * Miscellaneous configurable options | |
127 | */ | |
6d0f6bcf JCPV |
128 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
129 | #define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */ | |
130 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
131 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ | |
132 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
133 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
11edcfe2 | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */ |
136 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */ | |
11edcfe2 | 137 | |
6d0f6bcf | 138 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ |
11edcfe2 | 139 | |
6d0f6bcf | 140 | #define CONFIG_SYS_HZ 1000 |
11edcfe2 GL |
141 | |
142 | /* valid baudrates */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
11edcfe2 GL |
144 | |
145 | /*----------------------------------------------------------------------- | |
146 | * Stack sizes | |
147 | * | |
148 | * The stack sizes are set up in start.S using the settings below | |
149 | */ | |
150 | #define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */ | |
151 | ||
152 | /********************************** | |
153 | Support Clock Settings | |
154 | ********************************** | |
155 | Setting SYNC ASYNC | |
156 | ---------------------------------- | |
157 | 667_133_66 X O | |
158 | 533_133_66 O O | |
159 | 400_133_66 X O | |
160 | 400_100_50 O O | |
161 | **********************************/ | |
162 | ||
163 | /*#define CONFIG_CLK_667_133_66*/ | |
164 | #define CONFIG_CLK_533_133_66 | |
165 | /* | |
166 | #define CONFIG_CLK_400_100_50 | |
167 | #define CONFIG_CLK_400_133_66 | |
168 | #define CONFIG_SYNC_MODE | |
169 | */ | |
170 | ||
171 | /* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */ | |
172 | #define CONFIG_NR_DRAM_BANKS 1 | |
6d0f6bcf | 173 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ |
11edcfe2 GL |
174 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ |
175 | ||
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_FLASH_BASE 0x10000000 |
177 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
11edcfe2 GL |
178 | |
179 | /*----------------------------------------------------------------------- | |
180 | * FLASH and environment organization | |
181 | */ | |
6d0f6bcf | 182 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
11edcfe2 | 183 | /* AM29LV160B has 35 sectors, AM29LV800B - 19 */ |
6d0f6bcf | 184 | #define CONFIG_SYS_MAX_FLASH_SECT 40 |
11edcfe2 GL |
185 | |
186 | #define CONFIG_AMD_LV800 | |
6d0f6bcf | 187 | #define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */ |
11edcfe2 | 188 | /* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */ |
f9f692e2 | 189 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 190 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
11edcfe2 | 191 | #define CONFIG_FLASH_CFI_LEGACY |
6d0f6bcf | 192 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 |
11edcfe2 GL |
193 | |
194 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
195 | #define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
196 | #define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
11edcfe2 | 197 | |
0e8d1586 | 198 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
11edcfe2 GL |
199 | |
200 | /* | |
201 | * SMDK6400 board specific data | |
202 | */ | |
203 | ||
204 | #define CONFIG_IDENT_STRING " for SMDK6400" | |
205 | ||
206 | /* base address for uboot */ | |
6d0f6bcf | 207 | #define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000) |
11edcfe2 | 208 | /* total memory available to uboot */ |
6d0f6bcf | 209 | #define CONFIG_SYS_UBOOT_SIZE (1024 * 1024) |
11edcfe2 | 210 | |
b74ab737 GL |
211 | /* Put environment copies after the end of U-Boot owned RAM */ |
212 | #define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE) | |
213 | ||
11edcfe2 | 214 | #ifdef CONFIG_ENABLE_MMU |
6d0f6bcf | 215 | #define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 |
11edcfe2 GL |
216 | #define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \ |
217 | "bootm 0xc0018000" | |
218 | #else | |
6d0f6bcf | 219 | #define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE |
11edcfe2 GL |
220 | #define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ |
221 | "bootm 0x50018000" | |
222 | #endif | |
223 | ||
224 | /* NAND U-Boot load and start address */ | |
6d0f6bcf | 225 | #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000) |
11edcfe2 | 226 | |
0e8d1586 | 227 | #define CONFIG_ENV_OFFSET 0x0040000 |
11edcfe2 GL |
228 | |
229 | /* NAND configuration */ | |
6d0f6bcf JCPV |
230 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
231 | #define CONFIG_SYS_NAND_BASE 0x70200010 | |
6d0f6bcf | 232 | #define CONFIG_SYS_S3C_NAND_HWECC |
11edcfe2 | 233 | |
6d0f6bcf JCPV |
234 | #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ |
235 | #define CONFIG_SYS_NAND_WP 1 | |
236 | #define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */ | |
237 | #define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */ | |
11edcfe2 | 238 | |
6d0f6bcf JCPV |
239 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */ |
240 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */ | |
11edcfe2 | 241 | |
6d0f6bcf JCPV |
242 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ |
243 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ | |
11edcfe2 GL |
244 | |
245 | /* NAND chip page size */ | |
6d0f6bcf | 246 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 |
11edcfe2 | 247 | /* NAND chip block size */ |
6d0f6bcf | 248 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
11edcfe2 | 249 | /* NAND chip page per block count */ |
6d0f6bcf | 250 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
11edcfe2 | 251 | /* Location of the bad-block label */ |
6d0f6bcf | 252 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 |
11edcfe2 | 253 | /* Extra address cycle for > 128MiB */ |
6d0f6bcf | 254 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
11edcfe2 GL |
255 | |
256 | /* Size of the block protected by one OOB (Spare Area in Samsung terminology) */ | |
6d0f6bcf | 257 | #define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE |
11edcfe2 | 258 | /* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */ |
6d0f6bcf | 259 | #define CONFIG_SYS_NAND_ECCBYTES 4 |
11edcfe2 | 260 | /* Number of ECC-blocks per NAND page */ |
6d0f6bcf | 261 | #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) |
11edcfe2 | 262 | /* Size of a single OOB region */ |
6d0f6bcf | 263 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
11edcfe2 | 264 | /* Number of ECC bytes per page */ |
6d0f6bcf | 265 | #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) |
11edcfe2 | 266 | /* ECC byte positions */ |
6d0f6bcf | 267 | #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ |
11edcfe2 GL |
268 | 48, 49, 50, 51, 52, 53, 54, 55, \ |
269 | 56, 57, 58, 59, 60, 61, 62, 63} | |
270 | ||
271 | /* Boot configuration (define only one of next 3) */ | |
272 | #define CONFIG_BOOT_NAND | |
273 | /* None of these are currently implemented. Left from the original Samsung | |
274 | * version for reference | |
275 | #define CONFIG_BOOT_NOR | |
276 | #define CONFIG_BOOT_MOVINAND | |
277 | #define CONFIG_BOOT_ONENAND | |
278 | */ | |
279 | ||
280 | #define CONFIG_NAND | |
281 | #define CONFIG_NAND_S3C64XX | |
282 | /* Unimplemented or unsupported. See comment above. | |
283 | #define CONFIG_ONENAND | |
284 | #define CONFIG_MOVINAND | |
285 | */ | |
286 | ||
287 | /* Settings as above boot configuration */ | |
51bfee19 | 288 | #define CONFIG_ENV_IS_IN_NAND |
11edcfe2 | 289 | #define CONFIG_BOOTARGS "console=ttySAC,115200" |
11edcfe2 GL |
290 | |
291 | #if !defined(CONFIG_ENABLE_MMU) | |
292 | #define CONFIG_CMD_USB 1 | |
6d27bca1 | 293 | #define CONFIG_USB_S3C64XX |
11edcfe2 | 294 | #define CONFIG_USB_OHCI_NEW 1 |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000 |
296 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" | |
297 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 | |
298 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 | |
11edcfe2 GL |
299 | |
300 | #define CONFIG_USB_STORAGE 1 | |
301 | #endif | |
302 | #define CONFIG_DOS_PARTITION 1 | |
303 | ||
304 | #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU) | |
305 | # error "usb_ohci.c is currently broken with MMU enabled." | |
306 | #endif | |
307 | ||
308 | #endif /* __CONFIG_H */ |