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e21185ba CK |
1 | /* |
2 | * Copyright (C) 2011 Samsung Electronics | |
3 | * | |
393cb361 | 4 | * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. |
e21185ba | 5 | * |
1a459660 | 6 | * SPDX-License-Identifier: GPL-2.0+ |
e21185ba CK |
7 | */ |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
1d551100 SG |
12 | #include "exynos4-common.h" |
13 | ||
14 | #undef CONFIG_BOARD_COMMON | |
e30824f4 | 15 | #undef CONFIG_USB_GADGET_DWC2_OTG_PHY |
1d551100 | 16 | #undef CONFIG_REVISION_TAG |
1d551100 | 17 | |
e21185ba | 18 | /* High Level Configuration Options */ |
393cb361 | 19 | #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ |
e21185ba CK |
20 | #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ |
21 | ||
b3c5a49b CK |
22 | /* Mach Type */ |
23 | #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 | |
24 | ||
e21185ba | 25 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
e21185ba | 26 | |
e21185ba CK |
27 | /* Handling Sleep Mode*/ |
28 | #define S5P_CHECK_SLEEP 0x00000BAD | |
29 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
643be9c0 | 30 | #define S5P_CHECK_LPA 0xABAD0000 |
e21185ba | 31 | |
e21185ba | 32 | /* select serial console configuration */ |
e21185ba | 33 | #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ |
393cb361 | 34 | #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 |
e21185ba | 35 | |
e21185ba CK |
36 | /* allow to overwrite serial and ethaddr */ |
37 | #define CONFIG_ENV_OVERWRITE | |
38 | ||
5187d8dd | 39 | /* MMC SPL */ |
643be9c0 | 40 | #define CONFIG_SKIP_LOWLEVEL_INIT |
9b3ab1c9 | 41 | #define COPY_BL2_FNPTR_ADDR 0x00002488 |
e21185ba | 42 | |
8a00061e IS |
43 | #define CONFIG_SPL_TEXT_BASE 0x02021410 |
44 | ||
e21185ba CK |
45 | #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" |
46 | ||
47 | /* Miscellaneous configurable options */ | |
e21185ba | 48 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" |
e21185ba CK |
49 | /* memtest works on */ |
50 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
51 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) | |
52 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) | |
53 | ||
e21185ba CK |
54 | /* SMDKV310 has 4 bank of DRAM */ |
55 | #define CONFIG_NR_DRAM_BANKS 4 | |
56 | #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ | |
57 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
58 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
59 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
60 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
61 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
62 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
63 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
64 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
65 | ||
66 | /* FLASH and environment organization */ | |
e21185ba | 67 | |
e21185ba CK |
68 | #define CONFIG_CLK_1000_400_200 |
69 | ||
70 | /* MIU (Memory Interleaving Unit) */ | |
71 | #define CONFIG_MIU_2BIT_INTERLEAVED | |
72 | ||
e21185ba CK |
73 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
74 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ | |
75 | #define RESERVE_BLOCK_SIZE (512) | |
76 | #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
77 | #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) | |
e21185ba | 78 | |
643be9c0 RS |
79 | #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) |
80 | ||
81 | #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 | |
e21185ba | 82 | |
a187559e | 83 | /* U-Boot copy size from boot Media to DRAM.*/ |
e21185ba CK |
84 | #define COPY_BL2_SIZE 0x80000 |
85 | #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) | |
86 | #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) | |
87 | ||
88 | /* Ethernet Controllor Driver */ | |
89 | #ifdef CONFIG_CMD_NET | |
e21185ba CK |
90 | #define CONFIG_ENV_SROM_BANK 1 |
91 | #endif /*CONFIG_CMD_NET*/ | |
07407d97 | 92 | |
e21185ba | 93 | #endif /* __CONFIG_H */ |