[people/ms/u-boot.git] / include / configs / smmaco4.h

/*
 * (C) Copyright 2003-2006
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004-2005
 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU) */
#define CONFIG_TQM5200		1	/* ... on TQM5200 module */
#undef CONFIG_TQM5200_REV100		/*  define for revision 100 modules */

#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */

#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
#define BOOTFLAG_WARM		0x02	/* Software reboot	     */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION

/* POST support */
#define CONFIG_POST		(CFG_POST_MEMORY   | \
				 CFG_POST_CPU	   | \
				 CFG_POST_I2C)

#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP

#ifdef CONFIG_POST
#define CONFIG_CMD_DIAG
#endif


#define	CONFIG_TIMESTAMP		/* display image timestamps */

#if (TEXT_BASE == 0xFC000000)		/* Boot low */
#   define CFG_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"rootpath=/opt/eldk/ppc_6xx\0"					\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_self=run ramargs addip;"					\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"bootfile=/tftpboot/smmaco4/uImage\0"				\
	"load=tftp 200000 ${u-boot}\0"					\
	"u-boot=/tftpboot/smmaco4/u-boot.bin\0"				\
	"update=protect off FC000000 FC05FFFF;"				\
		"erase FC000000 FC05FFFF;"				\
		"cp.b 200000 FC000000 ${filesize};"			\
		"protect on FC000000 FC05FFFF\0"			\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

/*
 * IPB Bus clocking configuration.
 */
#define CFG_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
 * PCI Bus clocking configuration
 *
 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2	/* define for 66MHz speed */
#endif

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#ifdef CONFIG_TQM5200_REV100
#define CFG_I2C_MODULE		1	/* Select I2C module #1 for rev. 100 board */
#else
#define CFG_I2C_MODULE		2	/* Select I2C module #2 for all other revs */
#endif

/*
 * I2C clock frequency
 *
 * Please notice, that the resulting clock frequency could differ from the
 * configured value. This is because the I2C clock is derived from system
 * clock over a frequency divider with only a few divider values. U-boot
 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 * approximation allways lies below the configured value, never above.
 */
#define CFG_I2C_SPEED		100000 /* 100 kHz */
#define CFG_I2C_SLAVE		0x7F

/*
 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 * same configuration could be used.
 */
#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20

/*
 * Flash configuration
 */
#define CFG_FLASH_BASE		TEXT_BASE /* 0xFC000000 */

/* use CFI flash driver if no module variant is spezified */
#define CFG_FLASH_CFI		1	/* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
#define CFG_FLASH_BANKS_LIST	{ CFG_BOOTCS_START }
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_SIZE		0x04000000 /* 64 MByte */
#define CFG_MAX_FLASH_SECT	512	/* max num of sects on one chip */
#undef CFG_FLASH_USE_BUFFER_WRITE	/* not supported yet for AMD */

#if !defined(CFG_LOWBOOT)
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00760000 + 0x00800000)
#else	/* CFG_LOWBOOT */
#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00060000)
#endif	/* CFG_LOWBOOT */
#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

/* Dynamic MTD partition support */
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=TQM5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
						"1408k(kernel),"	\
						"2m(initrd),"		\
						"4m(small-fs),"		\
						"16m(big-fs),"		\
						"8m(misc)"

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE		0x10000
#define CFG_ENV_SECT_SIZE	0x20000
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define	CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

/*
 * Memory map
 */
#define CFG_MBAR		0xF0000000
#define CFG_SDRAM_BASE		0x00000000
#define CFG_DEFAULT_MBAR	0x80000000

/* Use ON-Chip SRAM until RAM will be available */
#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
#else
#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE
#endif


#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_BASE	TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#   define CFG_RAMBOOT		1
#endif

#define CFG_MONITOR_LEN		(384 << 10)	/* Reserve 384 kB for Monitor	*/
#define CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
/*
 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 */
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR		0x00

/*
 * GPIO configuration
 *
 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 *	Bit 0 (mask: 0x80000000): 1
 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 *	00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 *	01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 *	      Use for REV200 STK52XX boards. Do not use with REV100 modules
 *	      (because, there I2C1 is used as I2C bus)
 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 *	000 -> All PSC2 pins are GIOPs
 *	001 -> CAN1/2 on PSC2 pins
 *	       Use for REV100 STK52xx boards
 * use PSC6:
 *   on STK52xx:
 *	use as UART. Pins PSC6_0 to PSC6_3 are used.
 *	Bits 9:11 (mask: 0x00700000):
 *	   101 -> PSC6 : Extended POST test is not available
 *   on MINI-FAP and TQM5200_IB:
 *	use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 *	   000 -> PSC6 could not be used as UART, CODEC or IrDA
 *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 *   tests.
 */
#if defined (CONFIG_MINIFAP)
# define CFG_GPS_PORT_CONFIG	0x91000004
#elif defined (CONFIG_STK52XX)
# if defined (CONFIG_STK52XX_REV100)
#  define CFG_GPS_PORT_CONFIG	0x81500014
# else /* STK52xx REV200 and above */
#  if defined (CONFIG_TQM5200_REV100)
#   error TQM5200 REV100 not supported on STK52XX REV200 or above
#  else/* TQM5200 REV200 and above */
#   define CFG_GPS_PORT_CONFIG	0x91500004
#  endif
# endif
#else  /* TMQ5200 Inbetriebnahme-Board */
# define CFG_GPS_PORT_CONFIG	0x81000004
#endif

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	    */
#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS		16	/* max number of command args	*/
#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/

/* Enable an alternate, more extensive memory test */
#define CFG_ALT_MEMTEST

#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x100000	/* default load address */

#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */

#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#if defined(CONFIG_CMD_KGDB)
#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL		HID0_ICE
#else
#define CFG_HID0_INIT		0
#define CFG_HID0_FINAL		0
#endif

#define CFG_BOOTCS_START	CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG		0x0008DF30 /* for pci_clk  = 66 MHz */
#else
#define CFG_BOOTCS_CFG		0x0004DF30 /* for pci_clk = 33 MHz */
#endif
#define CFG_CS0_START		CFG_FLASH_BASE
#define CFG_CS0_SIZE		CFG_FLASH_SIZE

#define CFG_CS_BURST		0x00000000
#define CFG_CS_DEADCYCLE	0x33333311	/* 1 dead cycle for flash and SM501 */

#define CFG_RESET_ADDRESS	0xff000000

#endif /* __CONFIG_H */
Commit	Line	Data
075866d8 HS	1	/*
	2	* (C) Copyright 2003-2006
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2004-2005
	6	* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/*
	31	* High Level Configuration Options
	32	* (easy to change)
	33	*/
	34
	35	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	36	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	37	#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
	38	#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
	39
	40	#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
	41
	42	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	43	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	44
31d82672 BB	45	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	46
075866d8 HS	47	/*
	48	* Serial console configuration
	49	*/
	50	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	51	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
	52	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
	53
	54	/* Partitions */
	55	#define CONFIG_MAC_PARTITION
	56	#define CONFIG_DOS_PARTITION
	57	#define CONFIG_ISO_PARTITION
	58
	59	/* POST support */
	60	#define CONFIG_POST (CFG_POST_MEMORY \| \
	61	CFG_POST_CPU \| \
	62	CFG_POST_I2C)
	63
	64	#ifdef CONFIG_POST
075866d8 HS	65	/* preserve space for the post_word at end of on-chip SRAM */
075866d8 HS	66	#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
075866d8 HS	67	#endif
075866d8 HS	68
46da1e96	69
079a136c JL	70	/*
	71	* BOOTP options
	72	*/
	73	#define CONFIG_BOOTP_BOOTFILESIZE
	74	#define CONFIG_BOOTP_BOOTPATH
	75	#define CONFIG_BOOTP_GATEWAY
	76	#define CONFIG_BOOTP_HOSTNAME
	77
	78
075866d8	79	/*
46da1e96	80	* Command line configuration.
075866d8	81	*/
46da1e96 JL	82	#include <config_cmd_default.h>
	83	#define CONFIG_CMD_ASKENV
	84	#define CONFIG_CMD_DATE
	85	#define CONFIG_CMD_DHCP
	86	#define CONFIG_CMD_ECHO
	87	#define CONFIG_CMD_EEPROM
	88	#define CONFIG_CMD_I2C
	89	#define CONFIG_CMD_JFFS2
	90	#define CONFIG_CMD_MII
	91	#define CONFIG_CMD_NFS
	92	#define CONFIG_CMD_PING
46da1e96 JL	93	#define CONFIG_CMD_REGINFO
	94	#define CONFIG_CMD_SNTP
	95
af075ee9 JL	96	#ifdef CONFIG_POST
	97	#define CONFIG_CMD_DIAG
	98	#endif
	99
075866d8 HS	100
	101	#define CONFIG_TIMESTAMP /* display image timestamps */
	102
	103	#if (TEXT_BASE == 0xFC000000) /* Boot low */
	104	# define CFG_LOWBOOT 1
	105	#endif
	106
	107	/*
	108	* Autobooting
	109	*/
	110	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	111
	112	#define CONFIG_PREBOOT "echo;" \
32bf3d14	113	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
075866d8 HS	114	"echo"
	115
	116	#undef CONFIG_BOOTARGS
	117
	118	#define CONFIG_EXTRA_ENV_SETTINGS \
	119	"netdev=eth0\0" \
	120	"rootpath=/opt/eldk/ppc_6xx\0" \
	121	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	122	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	123	"nfsroot=${serverip}:${rootpath}\0" \
	124	"addip=setenv bootargs ${bootargs} " \
	125	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	126	":${hostname}:${netdev}:off panic=1\0" \
	127	"flash_self=run ramargs addip;" \
	128	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	129	"flash_nfs=run nfsargs addip;" \
	130	"bootm ${kernel_addr}\0" \
	131	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
	132	"bootfile=/tftpboot/smmaco4/uImage\0" \
	133	"load=tftp 200000 ${u-boot}\0" \
	134	"u-boot=/tftpboot/smmaco4/u-boot.bin\0" \
	135	"update=protect off FC000000 FC05FFFF;" \
	136	"erase FC000000 FC05FFFF;" \
	137	"cp.b 200000 FC000000 ${filesize};" \
	138	"protect on FC000000 FC05FFFF\0" \
	139	""
	140
	141	#define CONFIG_BOOTCOMMAND "run net_nfs"
	142
	143	/*
	144	* IPB Bus clocking configuration.
	145	*/
c99512d6	146	#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
075866d8	147
c99512d6	148	#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
075866d8 HS	149	/*
	150	* PCI Bus clocking configuration
	151	*
	152	* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
c99512d6 BS	153	* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
c99512d6 BS	154	* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
075866d8	155	*/
c99512d6	156	#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
075866d8 HS	157	#endif
	158
	159	/*
	160	* I2C configuration
	161	*/
	162	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
	163	#ifdef CONFIG_TQM5200_REV100
	164	#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
	165	#else
	166	#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
	167	#endif
	168
	169	/*
	170	* I2C clock frequency
	171	*
	172	* Please notice, that the resulting clock frequency could differ from the
	173	* configured value. This is because the I2C clock is derived from system
	174	* clock over a frequency divider with only a few divider values. U-boot
	175	* calculates the best approximation for CFG_I2C_SPEED. However the calculated
	176	* approximation allways lies below the configured value, never above.
	177	*/
	178	#define CFG_I2C_SPEED 100000 /* 100 kHz */
	179	#define CFG_I2C_SLAVE 0x7F
	180
	181	/*
	182	* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
	183	* also). For other EEPROMs configuration should be verified. On Mini-FAP the
	184	* EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
	185	* same configuration could be used.
	186	*/
	187	#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
	188	#define CFG_I2C_EEPROM_ADDR_LEN 2
	189	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	190	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	191
	192	/*
	193	* Flash configuration
	194	*/
	195	#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
	196
	197	/* use CFI flash driver if no module variant is spezified */
	198	#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
00b1883a	199	#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
075866d8 HS	200	#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
	201	#define CFG_FLASH_EMPTY_INFO
	202	#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
	203	#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
	204	#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
	205
	206	#if !defined(CFG_LOWBOOT)
	207	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
	208	#else /* CFG_LOWBOOT */
	209	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
	210	#endif /* CFG_LOWBOOT */
	211	#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
	212	(= chip selects) */
	213	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	214	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	215
	216	/* Dynamic MTD partition support */
	217	#define CONFIG_JFFS2_CMDLINE
	218	#define MTDIDS_DEFAULT "nor0=TQM5200-0"
	219	#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
	220	"1408k(kernel)," \
	221	"2m(initrd)," \
	222	"4m(small-fs)," \
	223	"16m(big-fs)," \
	224	"8m(misc)"
	225
	226	/*
	227	* Environment settings
	228	*/
5a1aceb0	229	#define CONFIG_ENV_IS_IN_FLASH 1
075866d8 HS	230	#define CFG_ENV_SIZE 0x10000
	231	#define CFG_ENV_SECT_SIZE 0x20000
	232	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
	233	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	234
	235	/*
	236	* Memory map
	237	*/
	238	#define CFG_MBAR 0xF0000000
	239	#define CFG_SDRAM_BASE 0x00000000
	240	#define CFG_DEFAULT_MBAR 0x80000000
	241
	242	/* Use ON-Chip SRAM until RAM will be available */
	243	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
	244	#ifdef CONFIG_POST
	245	/* preserve space for the post_word at end of on-chip SRAM */
	246	#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
	247	#else
	248	#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
	249	#endif
	250
	251
	252	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	253	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	254	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	255
	256	#define CFG_MONITOR_BASE TEXT_BASE
	257	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	258	# define CFG_RAMBOOT 1
	259	#endif
	260
	261	#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
	262	#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
	263	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	264
	265	/*
	266	* Ethernet configuration
	267	*/
	268	#define CONFIG_MPC5xxx_FEC 1
	269	/*
	270	* Define CONFIG_FEC_10MBIT to force FEC at 10Mb
	271	*/
	272	/* #define CONFIG_FEC_10MBIT 1 */
	273	#define CONFIG_PHY_ADDR 0x00
	274
	275	/*
	276	* GPIO configuration
	277	*
	278	* use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
	279	* Bit 0 (mask: 0x80000000): 1
	280	* use ALT CAN position: Bits 2-3 (mask: 0x30000000):
	281	* 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
	282	* 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
	283	* Use for REV200 STK52XX boards. Do not use with REV100 modules
	284	* (because, there I2C1 is used as I2C bus)
	285	* use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
	286	* use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
	287	* 000 -> All PSC2 pins are GIOPs
	288	* 001 -> CAN1/2 on PSC2 pins
	289	* Use for REV100 STK52xx boards
	290	* use PSC6:
	291	* on STK52xx:
	292	* use as UART. Pins PSC6_0 to PSC6_3 are used.
	293	* Bits 9:11 (mask: 0x00700000):
294	* 101 -> PSC6 : Extended POST test is not available
295	* on MINI-FAP and TQM5200_IB:
296	* use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
297	* 000 -> PSC6 could not be used as UART, CODEC or IrDA
298	* GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
299	* tests.
300	*/
301	#if defined (CONFIG_MINIFAP)
302	# define CFG_GPS_PORT_CONFIG 0x91000004
303	#elif defined (CONFIG_STK52XX)
304	# if defined (CONFIG_STK52XX_REV100)
305	# define CFG_GPS_PORT_CONFIG 0x81500014
306	# else /* STK52xx REV200 and above */
307	# if defined (CONFIG_TQM5200_REV100)
308	# error TQM5200 REV100 not supported on STK52XX REV200 or above
309	# else/* TQM5200 REV200 and above */
310	# define CFG_GPS_PORT_CONFIG 0x91500004
311	# endif
312	# endif
313	#else /* TMQ5200 Inbetriebnahme-Board */
314	# define CFG_GPS_PORT_CONFIG 0x81000004
315	#endif
316
317	/*
318	* RTC configuration
319	*/
320	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
321
322	/*
323	* Miscellaneous configurable options
324	*/
325	#define CFG_LONGHELP /* undef to save memory */
326	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
46da1e96	327	#if defined(CONFIG_CMD_KGDB)
075866d8 HS	328	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	329	#else
	330	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	331	#endif
	332	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	333	#define CFG_MAXARGS 16 /* max number of command args */
	334	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	335
	336	/* Enable an alternate, more extensive memory test */
	337	#define CFG_ALT_MEMTEST
	338
	339	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	340	#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	341
	342	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	343
	344	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	345
46da1e96 JL	346	#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
	347	#if defined(CONFIG_CMD_KGDB)
	348	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	349	#endif
	350
075866d8	351	/*
079a136c	352	* Enable loopw command.
075866d8 HS	353	*/
	354	#define CONFIG_LOOPW
	355
	356	/*
	357	* Various low-level settings
	358	*/
	359	#if defined(CONFIG_MPC5200)
	360	#define CFG_HID0_INIT HID0_ICE \| HID0_ICFI
	361	#define CFG_HID0_FINAL HID0_ICE
	362	#else
	363	#define CFG_HID0_INIT 0
	364	#define CFG_HID0_FINAL 0
	365	#endif
	366
	367	#define CFG_BOOTCS_START CFG_FLASH_BASE
	368	#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
c99512d6	369	#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
075866d8 HS	370	#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
	371	#else
	372	#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
	373	#endif
	374	#define CFG_CS0_START CFG_FLASH_BASE
	375	#define CFG_CS0_SIZE CFG_FLASH_SIZE
	376
	377	#define CFG_CS_BURST 0x00000000
	378	#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
	379
	380	#define CFG_RESET_ADDRESS 0xff000000
	381
	382	#endif /* __CONFIG_H */