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5095ee08 PM |
1 | /* |
2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
48275c96 DN |
6 | #ifndef __CONFIG_SOCFPGA_COMMON_H__ |
7 | #define __CONFIG_SOCFPGA_COMMON_H__ | |
5095ee08 | 8 | |
5095ee08 PM |
9 | /* Virtual target or real hardware */ |
10 | #undef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
11 | ||
5095ee08 PM |
12 | /* |
13 | * High level configuration | |
14 | */ | |
7287d5f0 | 15 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
5095ee08 PM |
16 | #define CONFIG_CLOCKS |
17 | ||
5095ee08 PM |
18 | #define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024) |
19 | ||
20 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
21 | ||
dc0a1a08 MV |
22 | /* add target to build it automatically upon "make" */ |
23 | #define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp" | |
24 | ||
5095ee08 PM |
25 | /* |
26 | * Memory configurations | |
27 | */ | |
28 | #define CONFIG_NR_DRAM_BANKS 1 | |
29 | #define PHYS_SDRAM_1 0x0 | |
0223a95c | 30 | #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) |
5095ee08 PM |
31 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 |
32 | #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE | |
1b259403 | 33 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
5095ee08 | 34 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
7599b53d | 35 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
1b259403 LFT |
36 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
37 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 | |
38 | #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ | |
39 | #endif | |
7599b53d MV |
40 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
41 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
42 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
43 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
5095ee08 PM |
44 | |
45 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
46 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
47 | #define CONFIG_SYS_TEXT_BASE 0x08000040 | |
48 | #else | |
49 | #define CONFIG_SYS_TEXT_BASE 0x01000040 | |
50 | #endif | |
51 | ||
52 | /* | |
53 | * U-Boot general configurations | |
54 | */ | |
55 | #define CONFIG_SYS_LONGHELP | |
56 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ | |
57 | #define CONFIG_SYS_PBSIZE \ | |
58 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
59 | /* Print buffer size */ | |
60 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ | |
61 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
62 | /* Boot argument buffer size */ | |
5095ee08 PM |
63 | #define CONFIG_AUTO_COMPLETE /* Command auto complete */ |
64 | #define CONFIG_CMDLINE_EDITING /* Command history etc */ | |
5095ee08 | 65 | |
ea082346 MV |
66 | #ifndef CONFIG_SYS_HOSTNAME |
67 | #define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD | |
68 | #endif | |
69 | ||
451e8241 DW |
70 | #define CONFIG_CMD_PXE |
71 | #define CONFIG_MENU | |
72 | ||
5095ee08 PM |
73 | /* |
74 | * Cache | |
75 | */ | |
5095ee08 PM |
76 | #define CONFIG_SYS_L2_PL310 |
77 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS | |
78 | ||
8a78ca9e MV |
79 | /* |
80 | * EPCS/EPCQx1 Serial Flash Controller | |
81 | */ | |
82 | #ifdef CONFIG_ALTERA_SPI | |
8a78ca9e | 83 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
8a78ca9e MV |
84 | /* |
85 | * The base address is configurable in QSys, each board must specify the | |
86 | * base address based on it's particular FPGA configuration. Please note | |
87 | * that the address here is incremented by 0x400 from the Base address | |
88 | * selected in QSys, since the SPI registers are at offset +0x400. | |
89 | * #define CONFIG_SYS_SPI_BASE 0xff240400 | |
90 | */ | |
91 | #endif | |
92 | ||
5095ee08 PM |
93 | /* |
94 | * Ethernet on SoC (EMAC) | |
95 | */ | |
96 | #if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) | |
5095ee08 PM |
97 | #define CONFIG_DW_ALTDESCRIPTOR |
98 | #define CONFIG_MII | |
99 | #define CONFIG_AUTONEG_TIMEOUT (15 * CONFIG_SYS_HZ) | |
5095ee08 PM |
100 | #define CONFIG_PHY_GIGE |
101 | #endif | |
102 | ||
103 | /* | |
104 | * FPGA Driver | |
105 | */ | |
1b259403 | 106 | #ifdef CONFIG_TARGET_SOCFPGA_GEN5 |
5095ee08 PM |
107 | #ifdef CONFIG_CMD_FPGA |
108 | #define CONFIG_FPGA | |
109 | #define CONFIG_FPGA_ALTERA | |
110 | #define CONFIG_FPGA_SOCFPGA | |
111 | #define CONFIG_FPGA_COUNT 1 | |
112 | #endif | |
1b259403 | 113 | #endif |
5095ee08 PM |
114 | /* |
115 | * L4 OSC1 Timer 0 | |
116 | */ | |
117 | /* This timer uses eosc1, whose clock frequency is fixed at any condition. */ | |
118 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS | |
119 | #define CONFIG_SYS_TIMER_COUNTS_DOWN | |
120 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) | |
121 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
122 | #define CONFIG_SYS_TIMER_RATE 2400000 | |
123 | #else | |
124 | #define CONFIG_SYS_TIMER_RATE 25000000 | |
125 | #endif | |
126 | ||
127 | /* | |
128 | * L4 Watchdog | |
129 | */ | |
130 | #ifdef CONFIG_HW_WATCHDOG | |
131 | #define CONFIG_DESIGNWARE_WATCHDOG | |
132 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS | |
133 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 | |
ea926511 | 134 | #define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 |
5095ee08 PM |
135 | #endif |
136 | ||
137 | /* | |
138 | * MMC Driver | |
139 | */ | |
140 | #ifdef CONFIG_CMD_MMC | |
5095ee08 | 141 | #define CONFIG_BOUNCE_BUFFER |
5095ee08 PM |
142 | /* FIXME */ |
143 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ | |
144 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ | |
145 | #endif | |
146 | ||
c339ea5b MV |
147 | /* |
148 | * NAND Support | |
149 | */ | |
150 | #ifdef CONFIG_NAND_DENALI | |
151 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
152 | #define CONFIG_SYS_NAND_MAX_CHIPS 1 | |
153 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
154 | #define CONFIG_NAND_DENALI_ECC_SIZE 512 | |
155 | #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS | |
156 | #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS | |
157 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_DATA_BASE + 0x10) | |
158 | #endif | |
159 | ||
7fb0f596 | 160 | /* |
ebcaf966 SR |
161 | * I2C support |
162 | */ | |
163 | #define CONFIG_SYS_I2C | |
ebcaf966 SR |
164 | #define CONFIG_SYS_I2C_BUS_MAX 4 |
165 | #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS | |
166 | #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS | |
167 | #define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS | |
168 | #define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS | |
169 | /* Using standard mode which the speed up to 100Kb/s */ | |
170 | #define CONFIG_SYS_I2C_SPEED 100000 | |
171 | #define CONFIG_SYS_I2C_SPEED1 100000 | |
172 | #define CONFIG_SYS_I2C_SPEED2 100000 | |
173 | #define CONFIG_SYS_I2C_SPEED3 100000 | |
174 | /* Address of device when used as slave */ | |
175 | #define CONFIG_SYS_I2C_SLAVE 0x02 | |
176 | #define CONFIG_SYS_I2C_SLAVE1 0x02 | |
177 | #define CONFIG_SYS_I2C_SLAVE2 0x02 | |
178 | #define CONFIG_SYS_I2C_SLAVE3 0x02 | |
179 | #ifndef __ASSEMBLY__ | |
180 | /* Clock supplied to I2C controller in unit of MHz */ | |
181 | unsigned int cm_get_l4_sp_clk_hz(void); | |
182 | #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000) | |
183 | #endif | |
ebcaf966 | 184 | |
7fb0f596 SR |
185 | /* |
186 | * QSPI support | |
187 | */ | |
7fb0f596 | 188 | /* Enable multiple SPI NOR flash manufacturers */ |
cbc9544d | 189 | #ifndef CONFIG_SPL_BUILD |
7fb0f596 | 190 | #define CONFIG_SPI_FLASH_MTD |
55b4312b MV |
191 | #define CONFIG_MTD_DEVICE |
192 | #define CONFIG_MTD_PARTITIONS | |
55702fe2 | 193 | #define MTDIDS_DEFAULT "nor0=ff705000.spi.0" |
cbc9544d | 194 | #endif |
7fb0f596 SR |
195 | /* QSPI reference clock */ |
196 | #ifndef __ASSEMBLY__ | |
197 | unsigned int cm_get_qspi_controller_clk_hz(void); | |
198 | #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() | |
199 | #endif | |
200 | #define CONFIG_CQSPI_DECODER 0 | |
57897c13 | 201 | #define CONFIG_BOUNCE_BUFFER |
7fb0f596 | 202 | |
0c745d00 MV |
203 | /* |
204 | * Designware SPI support | |
205 | */ | |
a6e73591 | 206 | |
5095ee08 PM |
207 | /* |
208 | * Serial Driver | |
209 | */ | |
5095ee08 PM |
210 | #define CONFIG_SYS_NS16550_SERIAL |
211 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
5095ee08 PM |
212 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET |
213 | #define CONFIG_SYS_NS16550_CLK 1000000 | |
1b259403 LFT |
214 | #elif defined(CONFIG_TARGET_SOCFPGA_GEN5) |
215 | #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS | |
5095ee08 | 216 | #define CONFIG_SYS_NS16550_CLK 100000000 |
1b259403 LFT |
217 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
218 | #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS | |
219 | #define CONFIG_SYS_NS16550_CLK 50000000 | |
5095ee08 PM |
220 | #endif |
221 | #define CONFIG_CONS_INDEX 1 | |
5095ee08 | 222 | |
20cadbbe MV |
223 | /* |
224 | * USB | |
225 | */ | |
20cadbbe | 226 | |
0223a95c MV |
227 | /* |
228 | * USB Gadget (DFU, UMS) | |
229 | */ | |
230 | #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) | |
01acd6ab | 231 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
0223a95c | 232 | |
55ce55fa | 233 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) |
0223a95c MV |
234 | #define DFU_DEFAULT_POLL_TIMEOUT 300 |
235 | ||
236 | /* USB IDs */ | |
e6c0bc06 SP |
237 | #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 |
238 | #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 | |
0223a95c MV |
239 | #endif |
240 | ||
5095ee08 PM |
241 | /* |
242 | * U-Boot environment | |
243 | */ | |
ead2fb29 | 244 | #if !defined(CONFIG_ENV_SIZE) |
451e8241 | 245 | #define CONFIG_ENV_SIZE (8 * 1024) |
ead2fb29 | 246 | #endif |
5095ee08 | 247 | |
79cc48e7 CLS |
248 | /* Environment for SDMMC boot */ |
249 | #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) | |
451e8241 DW |
250 | #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ |
251 | #define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ | |
79cc48e7 CLS |
252 | #endif |
253 | ||
ec8b7528 CLS |
254 | /* Environment for QSPI boot */ |
255 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) | |
256 | #define CONFIG_ENV_OFFSET 0x00100000 | |
257 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
258 | #endif | |
259 | ||
55702fe2 CLS |
260 | /* |
261 | * mtd partitioning for serial NOR flash | |
262 | * | |
263 | * device nor0 <ff705000.spi.0>, # parts = 6 | |
264 | * #: name size offset mask_flags | |
265 | * 0: u-boot 0x00100000 0x00000000 0 | |
266 | * 1: env1 0x00040000 0x00100000 0 | |
267 | * 2: env2 0x00040000 0x00140000 0 | |
268 | * 3: UBI 0x03e80000 0x00180000 0 | |
269 | * 4: boot 0x00e80000 0x00180000 0 | |
270 | * 5: rootfs 0x01000000 0x01000000 0 | |
271 | * | |
272 | */ | |
273 | #if defined(CONFIG_CMD_SF) && !defined(MTDPARTS_DEFAULT) | |
274 | #define MTDPARTS_DEFAULT "mtdparts=ff705000.spi.0:"\ | |
275 | "1m(u-boot)," \ | |
276 | "256k(env1)," \ | |
277 | "256k(env2)," \ | |
278 | "14848k(boot)," \ | |
279 | "16m(rootfs)," \ | |
280 | "-@1536k(UBI)\0" | |
281 | #endif | |
282 | ||
5095ee08 PM |
283 | /* |
284 | * SPL | |
34584d19 MV |
285 | * |
286 | * SRAM Memory layout: | |
287 | * | |
288 | * 0xFFFF_0000 ...... Start of SRAM | |
289 | * 0xFFFF_xxxx ...... Top of stack (grows down) | |
290 | * 0xFFFF_yyyy ...... Malloc area | |
291 | * 0xFFFF_zzzz ...... Global Data | |
292 | * 0xFFFF_FF00 ...... End of SRAM | |
5095ee08 PM |
293 | */ |
294 | #define CONFIG_SPL_FRAMEWORK | |
34584d19 | 295 | #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR |
1b259403 | 296 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE |
5095ee08 | 297 | |
d3f34e75 MV |
298 | /* SPL SDMMC boot support */ |
299 | #ifdef CONFIG_SPL_MMC_SUPPORT | |
300 | #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) | |
d3f34e75 | 301 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" |
451e8241 DW |
302 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
303 | #endif | |
304 | #else | |
305 | #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION | |
306 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 | |
d3f34e75 MV |
307 | #endif |
308 | #endif | |
5095ee08 | 309 | |
346d6f56 MV |
310 | /* SPL QSPI boot support */ |
311 | #ifdef CONFIG_SPL_SPI_SUPPORT | |
346d6f56 MV |
312 | #define CONFIG_SPL_SPI_LOAD |
313 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 | |
314 | #endif | |
315 | ||
c339ea5b MV |
316 | /* SPL NAND boot support */ |
317 | #ifdef CONFIG_SPL_NAND_SUPPORT | |
318 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
319 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
320 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 | |
321 | #endif | |
322 | ||
a717b811 DN |
323 | /* |
324 | * Stack setup | |
325 | */ | |
326 | #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR | |
327 | ||
451e8241 DW |
328 | /* Extra Environment */ |
329 | #ifndef CONFIG_SPL_BUILD | |
330 | #include <config_distro_defaults.h> | |
331 | ||
332 | #ifdef CONFIG_CMD_PXE | |
333 | #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) | |
334 | #else | |
335 | #define BOOT_TARGET_DEVICES_PXE(func) | |
336 | #endif | |
337 | ||
338 | #ifdef CONFIG_CMD_MMC | |
339 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) | |
340 | #else | |
341 | #define BOOT_TARGET_DEVICES_MMC(func) | |
342 | #endif | |
343 | ||
344 | #define BOOT_TARGET_DEVICES(func) \ | |
345 | BOOT_TARGET_DEVICES_MMC(func) \ | |
346 | BOOT_TARGET_DEVICES_PXE(func) \ | |
347 | func(DHCP, dhcp, na) | |
348 | ||
349 | #include <config_distro_bootcmd.h> | |
350 | ||
351 | #ifndef CONFIG_EXTRA_ENV_SETTINGS | |
352 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
353 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ | |
354 | "bootm_size=0xa000000\0" \ | |
355 | "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ | |
356 | "fdt_addr_r=0x02000000\0" \ | |
357 | "scriptaddr=0x02100000\0" \ | |
358 | "pxefile_addr_r=0x02200000\0" \ | |
359 | "ramdisk_addr_r=0x02300000\0" \ | |
360 | BOOTENV | |
361 | ||
362 | #endif | |
363 | #endif | |
364 | ||
48275c96 | 365 | #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ |