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ae9996c8 SR |
1 | /* |
2 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | #ifndef __CONFIG_SOCFPGA_SR1500_H__ | |
7 | #define __CONFIG_SOCFPGA_SR1500_H__ | |
8 | ||
9 | #include <asm/arch/base_addr_ac5.h> | |
10 | ||
ae9996c8 SR |
11 | #define CONFIG_FAT_WRITE |
12 | ||
13 | #define CONFIG_HW_WATCHDOG | |
14 | ||
ae9996c8 SR |
15 | /* Memory configurations */ |
16 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ | |
17 | ||
18 | /* Booting Linux */ | |
ae9996c8 SR |
19 | #define CONFIG_LOADADDR 0x01000000 |
20 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
ae9996c8 SR |
21 | |
22 | /* Ethernet on SoC (EMAC) */ | |
23 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII | |
24 | /* The PHY is autodetected, so no MII PHY address is needed here */ | |
25 | #define CONFIG_PHY_MARVELL | |
26 | #define PHY_ANEG_TIMEOUT 8000 | |
27 | ||
ae9996c8 SR |
28 | /* Environment */ |
29 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
30 | ||
31 | /* Enable SPI NOR flash reset, needed for SPI booting */ | |
32 | #define CONFIG_SPI_N25Q256A_RESET | |
33 | ||
34 | /* | |
35 | * Bootcounter | |
36 | */ | |
37 | #define CONFIG_BOOTCOUNT_LIMIT | |
38 | /* last 2 lwords in OCRAM */ | |
39 | #define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8 | |
40 | #define CONFIG_SYS_BOOTCOUNT_BE | |
41 | ||
ae9996c8 | 42 | /* Environment setting for SPI flash */ |
ae9996c8 SR |
43 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
44 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
45 | #define CONFIG_ENV_SIZE (16 * 1024) | |
93d9fc26 | 46 | #define CONFIG_ENV_OFFSET 0x000e0000 |
ae9996c8 SR |
47 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) |
48 | #define CONFIG_ENV_SPI_BUS 0 | |
49 | #define CONFIG_ENV_SPI_CS 0 | |
50 | #define CONFIG_ENV_SPI_MODE SPI_MODE_3 | |
93d9fc26 SR |
51 | #define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */ |
52 | #define CONFIG_SF_DEFAULT_SPEED 100000000 | |
53 | ||
54 | /* | |
55 | * The QSPI NOR flash layout on SR1500: | |
56 | * | |
57 | * 0000.0000 - 0003.ffff: SPL (4 times) | |
58 | * 0004.0000 - 000d.ffff: U-Boot | |
59 | * 000e.0000 - 000e.ffff: env1 | |
60 | * 000f.0000 - 000f.ffff: env2 | |
61 | */ | |
ae9996c8 | 62 | |
b72041cc MV |
63 | /* The rest of the configuration is shared */ |
64 | #include <configs/socfpga_common.h> | |
65 | ||
ae9996c8 | 66 | #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ |