[people/ms/u-boot.git] / include / configs / socfpga_sr1500.h

/*
 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_SR1500_H__
#define __CONFIG_SOCFPGA_SR1500_H__

#include <asm/arch/base_addr_ac5.h>

#define CONFIG_BOARD_EARLY_INIT_F

#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE

#define CONFIG_HW_WATCHDOG

/* U-Boot Commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MEMTEST
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PING
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TIME

/* Memory configurations */
#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */

/* Booting Linux */
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
#define CONFIG_LOADADDR		0x01000000
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */

/* Ethernet on SoC (EMAC) */
#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
/* The PHY is autodetected, so no MII PHY address is needed here */
#define CONFIG_PHY_MARVELL
#define PHY_ANEG_TIMEOUT	8000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"verify=n\0" \
	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
		"bootm ${loadaddr} - ${fdt_addr}\0" \
	"bootimage=zImage\0" \
	"fdt_addr=100\0" \
	"fdtimage=socfpga.dtb\0" \
		"fsloadcmd=ext2load\0" \
	"bootm ${loadaddr} - ${fdt_addr}\0" \
	"mmcroot=/dev/mmcblk0p2\0" \
	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${mmcroot} rw rootwait;" \
		"bootz ${loadaddr} - ${fdt_addr}\0" \
	"mmcload=mmc rescan;" \
		"load mmc 0:1 ${loadaddr} ${bootimage};" \
		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
	"qspiroot=/dev/mtdblock0\0" \
	"qspirootfstype=jffs2\0" \
	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
		"bootm ${loadaddr} - ${fdt_addr}\0" \
	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
		"ubifsload ${loadaddr} /boot/${bootimage} && " \
		"ubifsload ${fdt_addr} /boot/${fdtimage}\0"

/* Environment */
#define CONFIG_ENV_IS_IN_SPI_FLASH

/* Enable SPI NOR flash reset, needed for SPI booting */
#define CONFIG_SPI_N25Q256A_RESET

/*
 * Bootcounter
 */
#define CONFIG_BOOTCOUNT_LIMIT
/* last 2 lwords in OCRAM */
#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfffffff8
#define CONFIG_SYS_BOOTCOUNT_BE

/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

/* U-Boot payload is stored at offset 0x60000 */
#undef CONFIG_SYS_SPI_U_BOOT_OFFS
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x60000

/* Environment setting for SPI flash */
#undef CONFIG_ENV_SIZE
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_SIZE		(16 * 1024)
#define CONFIG_ENV_OFFSET	0x00040000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MODE	SPI_MODE_3
#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED

#endif	/* __CONFIG_SOCFPGA_SR1500_H__ */
Commit	Line	Data
ae9996c8 SR	1	/*
	2	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#ifndef __CONFIG_SOCFPGA_SR1500_H__
	7	#define __CONFIG_SOCFPGA_SR1500_H__
	8
	9	#include <asm/arch/base_addr_ac5.h>
	10
	11	#define CONFIG_BOARD_EARLY_INIT_F
	12
	13	#define CONFIG_SYS_NO_FLASH
	14	#define CONFIG_DOS_PARTITION
	15	#define CONFIG_FAT_WRITE
	16
	17	#define CONFIG_HW_WATCHDOG
	18
	19	/* U-Boot Commands */
	20	#define CONFIG_CMD_ASKENV
	21	#define CONFIG_CMD_BOOTZ
	22	#define CONFIG_CMD_CACHE
	23	#define CONFIG_CMD_DHCP
	24	#define CONFIG_CMD_EXT4
	25	#define CONFIG_CMD_EXT4_WRITE
	26	#define CONFIG_CMD_FAT
	27	#define CONFIG_CMD_FS_GENERIC
	28	#define CONFIG_CMD_GPIO
	29	#define CONFIG_CMD_GREPENV
	30	#define CONFIG_CMD_MEMTEST
	31	#define CONFIG_CMD_MII
	32	#define CONFIG_CMD_MMC
	33	#define CONFIG_CMD_PING
	34	#define CONFIG_CMD_SF
	35	#define CONFIG_CMD_SPI
	36	#define CONFIG_CMD_TIME
	37
	38	/* Memory configurations */
	39	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
	40
	41	/* Booting Linux */
	42	#define CONFIG_BOOTDELAY 3
	43	#define CONFIG_BOOTFILE "uImage"
	44	#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
	45	#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
	46	#define CONFIG_LOADADDR 0x01000000
	47	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	48	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	49
	50	/* Ethernet on SoC (EMAC) */
	51	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
	52	/* The PHY is autodetected, so no MII PHY address is needed here */
	53	#define CONFIG_PHY_MARVELL
	54	#define PHY_ANEG_TIMEOUT 8000
	55
ae9996c8 SR	56	#define CONFIG_EXTRA_ENV_SETTINGS \
	57	"verify=n\0" \
	58	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	59	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
	60	"bootm ${loadaddr} - ${fdt_addr}\0" \
	61	"bootimage=zImage\0" \
	62	"fdt_addr=100\0" \
	63	"fdtimage=socfpga.dtb\0" \
	64	"fsloadcmd=ext2load\0" \
	65	"bootm ${loadaddr} - ${fdt_addr}\0" \
	66	"mmcroot=/dev/mmcblk0p2\0" \
	67	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
	68	" root=${mmcroot} rw rootwait;" \
	69	"bootz ${loadaddr} - ${fdt_addr}\0" \
	70	"mmcload=mmc rescan;" \
	71	"load mmc 0:1 ${loadaddr} ${bootimage};" \
	72	"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
	73	"qspiroot=/dev/mtdblock0\0" \
	74	"qspirootfstype=jffs2\0" \
	75	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
	76	" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
eb45022c CLS	77	"bootm ${loadaddr} - ${fdt_addr}\0" \
	78	"ubiload=ubi part UBI && ubifsmount ubi0 && " \
	79	"ubifsload ${loadaddr} /boot/${bootimage} && " \
	80	"ubifsload ${fdt_addr} /boot/${fdtimage}\0"
ae9996c8 SR	81
	82	/* Environment */
	83	#define CONFIG_ENV_IS_IN_SPI_FLASH
	84
	85	/* Enable SPI NOR flash reset, needed for SPI booting */
	86	#define CONFIG_SPI_N25Q256A_RESET
	87
	88	/*
	89	* Bootcounter
	90	*/
	91	#define CONFIG_BOOTCOUNT_LIMIT
	92	/* last 2 lwords in OCRAM */
	93	#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
	94	#define CONFIG_SYS_BOOTCOUNT_BE
	95
	96	/* The rest of the configuration is shared */
	97	#include <configs/socfpga_common.h>
	98
	99	/* U-Boot payload is stored at offset 0x60000 */
	100	#undef CONFIG_SYS_SPI_U_BOOT_OFFS
	101	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
	102
	103	/* Environment setting for SPI flash */
	104	#undef CONFIG_ENV_SIZE
	105	#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
	106	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	107	#define CONFIG_ENV_SIZE (16 * 1024)
	108	#define CONFIG_ENV_OFFSET 0x00040000
	109	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
	110	#define CONFIG_ENV_SPI_BUS 0
	111	#define CONFIG_ENV_SPI_CS 0
	112	#define CONFIG_ENV_SPI_MODE SPI_MODE_3
	113	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	114
	115	#endif /* __CONFIG_SOCFPGA_SR1500_H__ */