[people/ms/u-boot.git] / include / configs / socrates.h

/*
 * (C) Copyright 2008
 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
 *
 * Wolfgang Denk <wd@denx.de>
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Socrates
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE			*/
#define CONFIG_E500		1	/* BOOKE e500 family		*/
#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
#define CONFIG_MPC8544		1
#define CONFIG_SOCRATES		1

#define CONFIG_PCI

#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/

#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * Only possible on E500 Version 2 or newer cores.
 */
#define CONFIG_ENABLE_36BIT_PHYS	1

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66666666
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
#define CONFIG_BTB			/* toggle branch predition	*/
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming	*/

#define CFG_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/

#undef	CFG_DRAM_TEST			/* memory test, takes time	*/
#define CFG_MEMTEST_START	0x00000000
#define CFG_MEMTEST_END		0x10000000

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT	0xFF700000	/* CCSRBAR Default	*/
#define CFG_CCSRBAR		0xE0000000	/* relocated CCSRBAR	*/
#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/

/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD

#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE	0xDeadBeef

#define CFG_DDR_SDRAM_BASE	0x00000000
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	2

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/

/* Hardcoded values, to use instead of SPD */
#define CFG_DDR_CS0_BNDS		0x0000000f
#define CFG_DDR_CS0_CONFIG		0x80010102
#define CFG_DDR_TIMING_0		0x00260802
#define CFG_DDR_TIMING_1		0x3935D322
#define CFG_DDR_TIMING_2		0x14904CC8
#define CFG_DDR_MODE			0x00480432
#define CFG_DDR_INTERVAL		0x030C0100
#define CFG_DDR_CONFIG_2		0x04400000
#define CFG_DDR_CONFIG			0xC3008000
#define CFG_DDR_CLK_CONTROL		0x03800000
#define CFG_SDRAM_SIZE			256 /* in Megs */

/*
 * Flash on the LocalBus
 */
#define CFG_LBC_CACHE_BASE	0xf0000000	/* Localbus cacheable	 */

#define CFG_FLASH0		0xFE000000
#define CFG_FLASH1		0xFC000000
#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH1, CFG_FLASH0 }

#define CFG_LBC_FLASH_BASE	CFG_FLASH1	/* Localbus flash start	*/
#define CFG_FLASH_BASE		CFG_LBC_FLASH_BASE /* start of FLASH	*/

#define CFG_BR0_PRELIM		0xfe001001	/* port size 16bit	*/
#define CFG_OR0_PRELIM		0xfe000ff7	/* 32MB Flash		*/
#define CFG_BR1_PRELIM		0xfc001001	/* port size 16bit	*/
#define CFG_OR1_PRELIM		0xfe000ff7	/* 32MB Flash		*/

#define CFG_FLASH_CFI				/* flash is CFI compat.	*/
#define CONFIG_FLASH_CFI_DRIVER			/* Use common CFI driver*/
#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/

#define CFG_MAX_FLASH_BANKS	2		/* number of banks	*/
#define CFG_MAX_FLASH_SECT	256		/* sectors per device	*/
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

#define CFG_LBC_LCRR		0x00030008    /* LB clock ratio reg	*/
#define CFG_LBC_LBCR		0x00000000    /* LB config reg		*/
#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer	*/
#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer presc.*/

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address	*/
#define CFG_INIT_RAM_END	0x4000		/* End used area in RAM	*/

#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256kB for Mon*/
#define CFG_MALLOC_LEN		(256 * 1024)	/* Reserved for malloc	*/

/* Serial Port */

#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)

#define CONFIG_BAUDRATE         115200

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define	CFG_PROMPT_HUSH_PS2	"> "
#endif


/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
#define CFG_I2C_OFFSET		0x3000

/* I2C RTC */
#define CONFIG_RTC_RX8025		/* Use Epson rx8025 rtc via i2c	*/
#define CFG_I2C_RTC_ADDR	0x32	/* at address 0x32		*/

/* I2C temp sensor */
/* Socrates uses Maxim's	DS75, which is compatible with LM75 */
#define CONFIG_DTT_LM75		1
#define CONFIG_DTT_SENSORS	{4}		/* Sensor addresses	*/
#define CFG_DTT_MAX_TEMP	125
#define CFG_DTT_LOW_TEMP	-55
#define CFG_DTT_HYSTERESIS	3
#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* necessary for the LM75 chip */
#define CFG_EEPROM_PAGE_WRITE_BITS	4

/*
 * General PCI
 * Memory space is mapped 1-1.
 */
#define CFG_PCI_PHYS		0x80000000	/* 1G PCI TLB */

/* PCI is clocked by the external source at 33 MHz */
#define CONFIG_PCI_CLK_FREQ	33000000
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
#define CFG_PCI1_IO_BASE	0xE2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M			*/

#if defined(CONFIG_PCI)
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#endif	/* CONFIG_PCI */


#define CONFIG_NET_MULTI	1
#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC3	1
#define CONFIG_TSEC3_NAME	"TSEC1"
#undef CONFIG_MPC85XX_FEC

#define TSEC1_PHY_ADDR		0
#define TSEC3_PHY_ADDR		1

#define TSEC1_PHYIDX		0
#define TSEC3_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC3_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0,1] */
#define CONFIG_ETHPRIME		"TSEC0"
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */

#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1

/*
 * Environment
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	0x20000 /* 128K(one sector) for env	*/
#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE		0x4000
#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB


#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_LOAD_ADDR	0x2000000	/* default load address		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/

#if defined(CONFIG_CMD_KGDB)
    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
    #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size	*/
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
#endif


#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/

#define CONFIG_BOOTDELAY 5		/* -1 disables auto-boot	*/

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"bootfile=$hostname/uImage\0"					\
	"netdev=eth0\0"							\
	"consdev=ttyS0\0"						\
	"hostname=socrates\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$serverip:$rootpath\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
		":$hostname:$netdev:off panic=1\0"			\
	"addcons=setenv bootargs $bootargs "				\
		"console=$consdev,$baudrate\0"				\
	"flash_self=run ramargs addip addcons;"				\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"tftp ${fdt_addr_r} ${fdt_file}; "			\
		"run nfsargs addip addcons;"				\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"fdt_file=$hostname/socrates.dtb\0"				\
	"fdt_addr_r=B00000\0"						\
	"fdt_addr=FC1E0000\0"						\
	"rootpath=/opt/eldk/ppc_85xxDP\0"				\
	"kernel_addr=FC000000\0"					\
	"kernel_addr_r=200000\0"					\
	"ramdisk_addr=FC200000\0"					\
	"ramdisk_addr_r=400000\0"					\
	"load=tftp 100000 $hostname/u-boot.bin\0"		\
	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"	\
		"cp.b 100000 fffc0000 40000;"			        \
		"setenv filesize;saveenv\0"				\
	"upd=run load update\0"						\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

/* USB support */
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_PCI_OHCI			1
#define CONFIG_PCI_OHCI_DEVNO		3 /* Number in PCI list */
#define CONFIG_PCI_EHCI_DEVNO		(CONFIG_PCI_OHCI_DEVNO / 2)
#define CFG_USB_OHCI_MAX_ROOT_PORTS	15
#define CFG_USB_OHCI_SLOT_NAME		"ohci_pci"
#define CFG_OHCI_SWAP_REG_ACCESS	1
#define CONFIG_DOS_PARTITION		1
#define CONFIG_USB_STORAGE		1

/* FPGA and NAND */
#define CFG_FPGA_BASE			0xc0000000
#define CFG_BR3_PRELIM			0xc0001881 /* UPMA, 32-bit */
#define CFG_OR3_PRELIM			0xfff00000  /* 1 MB */

#define CFG_NAND_BASE			(CFG_FPGA_BASE + 0x70)
#define CFG_MAX_NAND_DEVICE		1
#define NAND_MAX_CHIPS			1
#define CONFIG_CMD_NAND

#endif	/* __CONFIG_H */
Commit	Line	Data
5d108ac8 SP	1	/*
	2	* (C) Copyright 2008
	3	* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
	4	*
	5	* Wolfgang Denk <wd@denx.de>
	6	* Copyright 2004 Freescale Semiconductor.
	7	* (C) Copyright 2002,2003 Motorola,Inc.
	8	* Xianghua Xiao <X.Xiao@motorola.com>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/*
	30	* Socrates
	31	*/
	32
	33	#ifndef __CONFIG_H
	34	#define __CONFIG_H
	35
	36	/* High Level Configuration Options */
	37	#define CONFIG_BOOKE 1 /* BOOKE */
	38	#define CONFIG_E500 1 /* BOOKE e500 family */
	39	#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
	40	#define CONFIG_MPC8544 1
	41	#define CONFIG_SOCRATES 1
	42
	43	#define CONFIG_PCI
	44
	45	#define CONFIG_TSEC_ENET /* tsec ethernet support */
	46
	47	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	48
	49	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
	50
	51	/*
	52	* Only possible on E500 Version 2 or newer cores.
	53	*/
	54	#define CONFIG_ENABLE_36BIT_PHYS 1
	55
	56	/*
	57	* sysclk for MPC85xx
	58	*
	59	* Two valid values are:
	60	* 33000000
	61	* 66000000
	62	*
	63	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
	64	* is likely the desired value here, so that is now the default.
65	* The board, however, can run at 66MHz. In any event, this value
66	* must match the settings of some switches. Details can be found
67	* in the README.mpc85xxads.
68	*/
69
70	#ifndef CONFIG_SYS_CLK_FREQ
71	#define CONFIG_SYS_CLK_FREQ 66666666
72	#endif
73
74	/*
75	* These can be toggled for performance analysis, otherwise use default.
76	*/
77	#define CONFIG_L2_CACHE /* toggle L2 cache */
78	#define CONFIG_BTB /* toggle branch predition */
79	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
80
81	#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
82
83	#undef CFG_DRAM_TEST /* memory test, takes time */
84	#define CFG_MEMTEST_START 0x00000000
85	#define CFG_MEMTEST_END 0x10000000
86
87	/*
88	* Base addresses -- Note these are effective addresses where the
89	* actual resources get mapped (not physical addresses)
90	*/
91	#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
92	#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
93	#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */
94	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
95
be0bd823 KG	96	/* DDR Setup */
	97	#define CONFIG_FSL_DDR2
	98	#undef CONFIG_FSL_DDR_INTERACTIVE
	99	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	100	#define CONFIG_DDR_SPD
	101
	102	#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
	103	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	104
	105	#define CFG_DDR_SDRAM_BASE 0x00000000
5d108ac8	106	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
be0bd823 KG	107	#define CONFIG_VERY_BIG_RAM
	108
	109	#define CONFIG_NUM_DDR_CONTROLLERS 1
	110	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	111	#define CONFIG_CHIP_SELECTS_PER_CTRL 2
	112
	113	/* I2C addresses of SPD EEPROMs */
	114	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
5d108ac8 SP	115
	116	#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
	117
	118	/* Hardcoded values, to use instead of SPD */
	119	#define CFG_DDR_CS0_BNDS 0x0000000f
	120	#define CFG_DDR_CS0_CONFIG 0x80010102
	121	#define CFG_DDR_TIMING_0 0x00260802
	122	#define CFG_DDR_TIMING_1 0x3935D322
	123	#define CFG_DDR_TIMING_2 0x14904CC8
	124	#define CFG_DDR_MODE 0x00480432
	125	#define CFG_DDR_INTERVAL 0x030C0100
	126	#define CFG_DDR_CONFIG_2 0x04400000
	127	#define CFG_DDR_CONFIG 0xC3008000
	128	#define CFG_DDR_CLK_CONTROL 0x03800000
	129	#define CFG_SDRAM_SIZE 256 /* in Megs */
	130
5d108ac8 SP	131	/*
	132	* Flash on the LocalBus
	133	*/
	134	#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
	135
	136	#define CFG_FLASH0 0xFE000000
	137	#define CFG_FLASH1 0xFC000000
	138	#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
	139
	140	#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
	141	#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
	142
	143	#define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */
	144	#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */
	145	#define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */
	146	#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */
	147
	148	#define CFG_FLASH_CFI /* flash is CFI compat. */
00b1883a	149	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
5d108ac8 SP	150	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
	151
	152	#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
e18575d5	153	#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
5d108ac8 SP	154	#undef CFG_FLASH_CHECKSUM
	155	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	156	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	157
	158	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	159
	160	#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
	161	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	162	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	163	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
	164
	165	#define CONFIG_L1_INIT_RAM
	166	#define CFG_INIT_RAM_LOCK 1
	167	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
	168	#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
	169
	170	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
	171	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	172	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	173
	174	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
fd51b0e0	175	#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
5d108ac8 SP	176
	177	/* Serial Port */
	178
	179	#define CONFIG_CONS_INDEX 1
	180	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	181	#define CFG_NS16550
	182	#define CFG_NS16550_SERIAL
	183	#define CFG_NS16550_REG_SIZE 1
	184	#define CFG_NS16550_CLK get_bus_freq(0)
	185
	186	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
	187	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
	188
	189	#define CONFIG_BAUDRATE 115200
	190
	191	#define CFG_BAUDRATE_TABLE \
	192	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	193
	194	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
	195	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
	196	#ifdef CFG_HUSH_PARSER
	197	#define CFG_PROMPT_HUSH_PS2 "> "
	198	#endif
	199
	200
	201	/*
	202	* I2C
	203	*/
	204	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	205	#define CONFIG_HARD_I2C /* I2C with hardware support */
	206	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	207	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	208	#define CFG_I2C_SLAVE 0x7F
	209	#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
	210	#define CFG_I2C_OFFSET 0x3000
	211
	212	/* I2C RTC */
e18575d5 SP	213	#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
e18575d5 SP	214	#define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */
5d108ac8	215
2f7468ae SP	216	/* I2C temp sensor */
	217	/* Socrates uses Maxim's DS75, which is compatible with LM75 */
	218	#define CONFIG_DTT_LM75 1
	219	#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
	220	#define CFG_DTT_MAX_TEMP 125
	221	#define CFG_DTT_LOW_TEMP -55
	222	#define CFG_DTT_HYSTERESIS 3
	223	#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */
	224	#define CFG_EEPROM_PAGE_WRITE_BITS 4
	225
5d108ac8 SP	226	/*
	227	* General PCI
	228	* Memory space is mapped 1-1.
	229	*/
	230	#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
	231
5e1882df SP	232	/* PCI is clocked by the external source at 33 MHz */
5e1882df SP	233	#define CONFIG_PCI_CLK_FREQ 33000000
5d108ac8 SP	234	#define CFG_PCI1_MEM_BASE 0x80000000
	235	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	236	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	237	#define CFG_PCI1_IO_BASE 0xE2000000
	238	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
	239	#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
	240
	241	#if defined(CONFIG_PCI)
5d108ac8	242	#define CONFIG_PCI_PNP /* do pci plug-and-play */
d39e6851	243	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
5d108ac8 SP	244	#endif /* CONFIG_PCI */
	245
	246
	247	#define CONFIG_NET_MULTI 1
	248	#define CONFIG_MII 1 /* MII PHY management */
	249	#define CONFIG_TSEC1 1
	250	#define CONFIG_TSEC1_NAME "TSEC0"
2f845dc2 SP	251	#define CONFIG_TSEC3 1
2f845dc2 SP	252	#define CONFIG_TSEC3_NAME "TSEC1"
5d108ac8 SP	253	#undef CONFIG_MPC85XX_FEC
	254
	255	#define TSEC1_PHY_ADDR 0
2f845dc2	256	#define TSEC3_PHY_ADDR 1
5d108ac8 SP	257
5d108ac8 SP	258	#define TSEC1_PHYIDX 0
2f845dc2	259	#define TSEC3_PHYIDX 0
5d108ac8	260	#define TSEC1_FLAGS TSEC_GIGABIT
2f845dc2	261	#define TSEC3_FLAGS TSEC_GIGABIT
5d108ac8	262
2f845dc2	263	/* Options are: TSEC[0,1] */
5d108ac8 SP	264	#define CONFIG_ETHPRIME "TSEC0"
	265	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	266
e18575d5 SP	267	#define CONFIG_HAS_ETH0
	268	#define CONFIG_HAS_ETH1
	269
5d108ac8 SP	270	/*
	271	* Environment
	272	*/
	273	#define CFG_ENV_IS_IN_FLASH 1
	274	#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
	275	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
	276	#define CFG_ENV_SIZE 0x4000
	277	#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
	278	#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
	279
	280	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	281	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	282
	283	#define CONFIG_TIMESTAMP /* Print image info with ts */
	284
	285
	286	/*
	287	* BOOTP options
	288	*/
	289	#define CONFIG_BOOTP_BOOTFILESIZE
	290	#define CONFIG_BOOTP_BOOTPATH
	291	#define CONFIG_BOOTP_GATEWAY
	292	#define CONFIG_BOOTP_HOSTNAME
	293
	294
	295	/*
	296	* Command line configuration.
	297	*/
	298	#include <config_cmd_default.h>
	299
	300	#define CONFIG_CMD_DATE
	301	#define CONFIG_CMD_DHCP
2f7468ae	302	#define CONFIG_CMD_DTT
5d108ac8 SP	303	#undef CONFIG_CMD_EEPROM
	304	#define CONFIG_CMD_I2C
	305	#define CONFIG_CMD_MII
	306	#define CONFIG_CMD_NFS
	307	#define CONFIG_CMD_PING
5d108ac8	308	#define CONFIG_CMD_SNTP
791e1dba	309	#define CONFIG_CMD_USB
5d108ac8 SP	310
	311
	312	#if defined(CONFIG_PCI)
	313	#define CONFIG_CMD_PCI
	314	#endif
	315
	316
	317	#undef CONFIG_WATCHDOG /* watchdog disabled */
	318
	319	/*
	320	* Miscellaneous configurable options
	321	*/
	322	#define CFG_LONGHELP /* undef to save memory */
	323	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	324	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	325
	326	#if defined(CONFIG_CMD_KGDB)
	327	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	328	#else
	329	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	330	#endif
	331
	332	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
	333	#define CFG_MAXARGS 16 /* max number of command args */
	334	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	335	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	336
	337	/*
	338	* For booting Linux, the board info and command line data
	339	* have to be in the first 8 MB of memory, since this is
	340	* the maximum mapped by the Linux kernel during initialization.
	341	*/
	342	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	343
	344	/*
	345	* Internal Definitions
	346	*
	347	* Boot Flags
	348	*/
	349	#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
	350	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	351
	352	#if defined(CONFIG_CMD_KGDB)
	353	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
	354	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	355	#endif
	356
	357
	358	#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
	359
	360	#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
	361
	362	#define CONFIG_PREBOOT "echo;" \
	363	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	364	"echo"
	365
	366	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	367
	368	#define CONFIG_EXTRA_ENV_SETTINGS \
83e9d7a2	369	"bootfile=$hostname/uImage\0" \
5d108ac8 SP	370	"netdev=eth0\0" \
5d108ac8 SP	371	"consdev=ttyS0\0" \
83e9d7a2	372	"hostname=socrates\0" \
5d108ac8 SP	373	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	374	"nfsroot=$serverip:$rootpath\0" \
	375	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	376	"addip=setenv bootargs $bootargs " \
	377	"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
	378	":$hostname:$netdev:off panic=1\0" \
	379	"addcons=setenv bootargs $bootargs " \
	380	"console=$consdev,$baudrate\0" \
5d108ac8	381	"flash_self=run ramargs addip addcons;" \
e18575d5 SP	382	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
	383	"flash_nfs=run nfsargs addip addcons;" \
	384	"bootm ${kernel_addr} - ${fdt_addr}\0" \
	385	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	386	"tftp ${fdt_addr_r} ${fdt_file}; " \
	387	"run nfsargs addip addcons;" \
	388	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
d39e6851	389	"fdt_file=$hostname/socrates.dtb\0" \
e18575d5 SP	390	"fdt_addr_r=B00000\0" \
e18575d5 SP	391	"fdt_addr=FC1E0000\0" \
d39e6851	392	"rootpath=/opt/eldk/ppc_85xxDP\0" \
e18575d5 SP	393	"kernel_addr=FC000000\0" \
	394	"kernel_addr_r=200000\0" \
	395	"ramdisk_addr=FC200000\0" \
	396	"ramdisk_addr_r=400000\0" \
83e9d7a2	397	"load=tftp 100000 $hostname/u-boot.bin\0" \
5d108ac8 SP	398	"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
	399	"cp.b 100000 fffc0000 40000;" \
	400	"setenv filesize;saveenv\0" \
	401	"upd=run load update\0" \
	402	""
	403	#define CONFIG_BOOTCOMMAND "run flash_self"
	404
e18575d5 SP	405	/* pass open firmware flat tree */
	406	#define CONFIG_OF_LIBFDT 1
	407	#define CONFIG_OF_BOARD_SETUP 1
	408
791e1dba SP	409	/* USB support */
	410	#define CONFIG_USB_OHCI_NEW 1
	411	#define CONFIG_PCI_OHCI 1
	412	#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
e90fb6af	413	#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
791e1dba SP	414	#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
	415	#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
	416	#define CFG_OHCI_SWAP_REG_ACCESS 1
	417	#define CONFIG_DOS_PARTITION 1
	418	#define CONFIG_USB_STORAGE 1
	419
59abd15b SP	420	/* FPGA and NAND */
	421	#define CFG_FPGA_BASE 0xc0000000
	422	#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
	423	#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */
fd51b0e0 SP	424
	425	#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70)
	426	#define CFG_MAX_NAND_DEVICE 1
	427	#define NAND_MAX_CHIPS 1
	428	#define CONFIG_CMD_NAND
	429
5d108ac8	430	#endif /* __CONFIG_H */