[people/ms/u-boot.git] / include / configs / spear-common.h

/*
 * (C) Copyright 2009
 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SPEAR_COMMON_H
#define _SPEAR_COMMON_H
/*
 * Common configurations used for both spear3xx as well as spear6xx
 */

/* U-Boot Load Address */
#define CONFIG_SYS_TEXT_BASE			0x00700000

/* Ethernet driver configuration */
#define CONFIG_MII
#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */
#define CONFIG_PHY_GIGE			/* Include GbE speed/duplex detection */

/* USBD driver configuration */
#if defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DW_UDC
#define CONFIG_USB_DEVICE
#define CONFIG_USBD_HS
#define CONFIG_USB_TTY

#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"

#endif

#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"

/* I2C driver configuration */
#define CONFIG_SYS_I2C
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE			0xD0200000
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_I2C_BASE			0xD0180000
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_I2C_BASE			0xD0180000
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_I2C_BASE			0xD0180000
#endif
#define CONFIG_SYS_I2C_SPEED			400000
#define CONFIG_SYS_I2C_SLAVE			0x02

#define CONFIG_I2C_CHIPADDRESS			0x50

/* Timer, HZ specific defines */

/* Flash configuration */
#if defined(CONFIG_FLASH_PNOR)
#define CONFIG_SPEAR_EMI
#else
#define CONFIG_ST_SMI
#endif

#if defined(CONFIG_ST_SMI)

#define CONFIG_SYS_MAX_FLASH_BANKS		2
#define CONFIG_SYS_FLASH_BASE			0xF8000000
#define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
						CONFIG_SYS_CS1_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_SECT		128

#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)

#endif

/*
 * Serial Configuration (PL011)
 * CONFIG_PL01x_PORTS is defined in specific files
 */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
#define CONFIG_CONS_INDEX			0
#define CONFIG_BAUDRATE				115200
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
						57600, 115200 }

#define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NAND FLASH Configuration */
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_ONFI_DETECTION

/*
 * Command support defines
 */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVES

/*
 * Default Environment Varible definitions
 */
#define CONFIG_ENV_OVERWRITE

/*
 * U-Boot Environment placing definitions.
 */
#if defined(CONFIG_ENV_IS_IN_FLASH)
#ifdef CONFIG_ST_SMI
/*
 * Environment is in serial NOR flash
 */
#define CONFIG_SYS_MONITOR_LEN			0x00040000
#define CONFIG_ENV_SECT_SIZE			0x00010000
#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "

#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"

#elif defined(CONFIG_SPEAR_EMI)
/*
 * Environment is in parallel NOR flash
 */
#define CONFIG_SYS_MONITOR_LEN			0x00060000
#define CONFIG_ENV_SECT_SIZE			0x00020000
#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "

#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
						"0x4C0000; bootm 0x1600000"
#endif

#define CONFIG_ENV_ADDR				(CONFIG_SYS_FLASH_BASE + \
						CONFIG_SYS_MONITOR_LEN)
#elif defined(CONFIG_ENV_IS_IN_NAND)
/*
 * Environment is in NAND
 */

#define CONFIG_ENV_OFFSET			0x60000
#define CONFIG_ENV_RANGE			0x10000
#define CONFIG_FSMTDBLK				"/dev/mtdblock7 "

#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
						"0x80000 0x4C0000; " \
						"bootm 0x1600000"
#endif

#define CONFIG_BOOTARGS				"console=ttyAMA0,115200 " \
						"mem=128M " \
						"root="CONFIG_FSMTDBLK \
						"rootfstype=jffs2"

#define CONFIG_NFSBOOTCOMMAND						\
	"bootp; "							\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$(serverip):$(rootpath) "				\
	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
			"$(netmask):$(hostname):$(netdev):off "		\
			"console=ttyAMA0,115200 $(othbootargs);"	\
	"bootm; "

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=ttyAMA0,115200 $(othbootargs);"		\
	CONFIG_BOOTCOMMAND

#define CONFIG_ENV_SIZE				0x02000
#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE

/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_MEMTEST_START		0x00800000
#define CONFIG_SYS_MEMTEST_END			0x04000000
#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_CBSIZE			256
#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS			16
#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR			0x00800000
#define CONFIG_SYS_CONSOLE_INFO_QUIET

#define CONFIG_SYS_FLASH_EMPTY_INFO

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS			1
#define PHYS_SDRAM_1				0x00000000
#define PHYS_SDRAM_1_MAXSIZE			0x40000000

#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
#define CONFIG_SYS_INIT_RAM_SIZE		0x2000

#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#endif
Commit	Line	Data
566c9c16 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
566c9c16 VK	6	*/
	7
	8	#ifndef _SPEAR_COMMON_H
	9	#define _SPEAR_COMMON_H
	10	/*
	11	* Common configurations used for both spear3xx as well as spear6xx
	12	*/
	13
a187559e	14	/* U-Boot Load Address */
f273e5b2 VK	15	#define CONFIG_SYS_TEXT_BASE 0x00700000
f273e5b2 VK	16
deb00562 VK	17	/* Ethernet driver configuration */
deb00562 VK	18	#define CONFIG_MII
deb00562	19	#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
ef76025a	20	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
deb00562	21
566c9c16	22	/* USBD driver configuration */
b884236e	23	#if defined(CONFIG_SPEAR_USBTTY)
2721551a	24	#define CONFIG_DW_UDC
566c9c16	25	#define CONFIG_USB_DEVICE
50726684	26	#define CONFIG_USBD_HS
566c9c16 VK	27	#define CONFIG_USB_TTY
	28
	29	#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
	30	#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
	31
b884236e VK	32	#endif
b884236e VK	33
566c9c16 VK	34	#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
	35
	36	/* I2C driver configuration */
678398b1	37	#define CONFIG_SYS_I2C
f93f589c AB	38	#if defined(CONFIG_SPEAR600)
	39	#define CONFIG_SYS_I2C_BASE 0xD0200000
	40	#elif defined(CONFIG_SPEAR300)
	41	#define CONFIG_SYS_I2C_BASE 0xD0180000
	42	#elif defined(CONFIG_SPEAR310)
	43	#define CONFIG_SYS_I2C_BASE 0xD0180000
	44	#elif defined(CONFIG_SPEAR320)
	45	#define CONFIG_SYS_I2C_BASE 0xD0180000
	46	#endif
566c9c16 VK	47	#define CONFIG_SYS_I2C_SPEED 400000
	48	#define CONFIG_SYS_I2C_SLAVE 0x02
	49
	50	#define CONFIG_I2C_CHIPADDRESS 0x50
	51
	52	/* Timer, HZ specific defines */
566c9c16 VK	53
	54	/* Flash configuration */
	55	#if defined(CONFIG_FLASH_PNOR)
9b382b43	56	#define CONFIG_SPEAR_EMI
566c9c16	57	#else
f3fcf92d	58	#define CONFIG_ST_SMI
566c9c16 VK	59	#endif
566c9c16 VK	60
f3fcf92d	61	#if defined(CONFIG_ST_SMI)
566c9c16 VK	62
566c9c16 VK	63	#define CONFIG_SYS_MAX_FLASH_BANKS 2
bc0bdf4c AV	64	#define CONFIG_SYS_FLASH_BASE 0xF8000000
	65	#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
	66	#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
566c9c16 VK	67	#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
	68	CONFIG_SYS_CS1_FLASH_BASE}
	69	#define CONFIG_SYS_MAX_FLASH_SECT 128
	70
566c9c16 VK	71	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
	72	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
	73
	74	#endif
	75
	76	/*
	77	* Serial Configuration (PL011)
	78	* CONFIG_PL01x_PORTS is defined in specific files
	79	*/
	80	#define CONFIG_PL011_SERIAL
	81	#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
	82	#define CONFIG_CONS_INDEX 0
	83	#define CONFIG_BAUDRATE 115200
	84	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
	85	57600, 115200 }
	86
	87	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	88
	89	/* NAND FLASH Configuration */
1fa943b9	90	#define CONFIG_SYS_NAND_SELF_INIT
a39fcfb2 SH	91	#define CONFIG_MTD_DEVICE
a39fcfb2 SH	92	#define CONFIG_MTD_PARTITIONS
1fa943b9	93	#define CONFIG_NAND_FSMC
566c9c16	94	#define CONFIG_SYS_MAX_NAND_DEVICE 1
bc912e78	95	#define CONFIG_SYS_NAND_ONFI_DETECTION
566c9c16 VK	96
	97	/*
	98	* Command support defines
	99	*/
566c9c16 VK	100	#define CONFIG_CMD_NAND
566c9c16 VK	101	#define CONFIG_CMD_ENV
566c9c16 VK	102	#define CONFIG_CMD_SAVES
566c9c16 VK	103
566c9c16 VK	104	/*
	105	* Default Environment Varible definitions
	106	*/
566c9c16 VK	107	#define CONFIG_ENV_OVERWRITE
	108
	109	/*
	110	* U-Boot Environment placing definitions.
	111	*/
	112	#if defined(CONFIG_ENV_IS_IN_FLASH)
f3fcf92d	113	#ifdef CONFIG_ST_SMI
566c9c16 VK	114	/*
	115	* Environment is in serial NOR flash
	116	*/
	117	#define CONFIG_SYS_MONITOR_LEN 0x00040000
	118	#define CONFIG_ENV_SECT_SIZE 0x00010000
1b7935cd	119	#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
566c9c16 VK	120
	121	#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
	122
	123	#elif defined(CONFIG_SPEAR_EMI)
	124	/*
	125	* Environment is in parallel NOR flash
	126	*/
	127	#define CONFIG_SYS_MONITOR_LEN 0x00060000
	128	#define CONFIG_ENV_SECT_SIZE 0x00020000
	129	#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
	130
	131	#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
	132	"0x4C0000; bootm 0x1600000"
	133	#endif
	134
0296f159	135	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
566c9c16 VK	136	CONFIG_SYS_MONITOR_LEN)
	137	#elif defined(CONFIG_ENV_IS_IN_NAND)
	138	/*
	139	* Environment is in NAND
	140	*/
	141
	142	#define CONFIG_ENV_OFFSET 0x60000
	143	#define CONFIG_ENV_RANGE 0x10000
1b7935cd	144	#define CONFIG_FSMTDBLK "/dev/mtdblock7 "
566c9c16 VK	145
	146	#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
	147	"0x80000 0x4C0000; " \
	148	"bootm 0x1600000"
	149	#endif
	150
1b7935cd VK	151	#define CONFIG_BOOTARGS "console=ttyAMA0,115200 " \
1b7935cd VK	152	"mem=128M " \
566c9c16 VK	153	"root="CONFIG_FSMTDBLK \
	154	"rootfstype=jffs2"
	155
1b7935cd VK	156	#define CONFIG_NFSBOOTCOMMAND \
	157	"bootp; " \
	158	"setenv bootargs root=/dev/nfs rw " \
	159	"nfsroot=$(serverip):$(rootpath) " \
	160	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	161	"$(netmask):$(hostname):$(netdev):off " \
	162	"console=ttyAMA0,115200 $(othbootargs);" \
	163	"bootm; "
	164
	165	#define CONFIG_RAMBOOTCOMMAND \
	166	"setenv bootargs root=/dev/ram rw " \
	167	"console=ttyAMA0,115200 $(othbootargs);" \
	168	CONFIG_BOOTCOMMAND
	169
566c9c16	170	#define CONFIG_ENV_SIZE 0x02000
0296f159	171	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
566c9c16 VK	172
566c9c16 VK	173	/* Miscellaneous configurable options */
962d026b	174	#define CONFIG_ARCH_CPU_INIT
0b7ff3f4	175	#define CONFIG_BOARD_EARLY_INIT_F
962d026b	176	#define CONFIG_DISPLAY_CPUINFO
566c9c16	177	#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
9b382b43 AV	178	#define CONFIG_CMDLINE_TAG
	179	#define CONFIG_SETUP_MEMORY_TAGS
	180	#define CONFIG_MISC_INIT_R
566c9c16 VK	181
	182	#define CONFIG_SYS_MEMTEST_START 0x00800000
	183	#define CONFIG_SYS_MEMTEST_END 0x04000000
	184	#define CONFIG_SYS_MALLOC_LEN (1024*1024)
566c9c16	185	#define CONFIG_SYS_LONGHELP
566c9c16 VK	186	#define CONFIG_CMDLINE_EDITING
	187	#define CONFIG_SYS_CBSIZE 256
	188	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	189	sizeof(CONFIG_SYS_PROMPT) + 16)
	190	#define CONFIG_SYS_MAXARGS 16
	191	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	192	#define CONFIG_SYS_LOAD_ADDR 0x00800000
9b382b43	193	#define CONFIG_SYS_CONSOLE_INFO_QUIET
566c9c16	194
cc4b5a34 VK	195	#define CONFIG_SYS_FLASH_EMPTY_INFO
cc4b5a34 VK	196
566c9c16 VK	197	/* Physical Memory Map */
	198	#define CONFIG_NR_DRAM_BANKS 1
	199	#define PHYS_SDRAM_1 0x00000000
	200	#define PHYS_SDRAM_1_MAXSIZE 0x40000000
	201
a39fcfb2 SH	202	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	203	#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
	204	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
	205
	206	#define CONFIG_SYS_INIT_SP_OFFSET \
	207	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	208
	209	#define CONFIG_SYS_INIT_SP_ADDR \
	210	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	211
566c9c16	212	#endif