[people/ms/u-boot.git] / include / configs / spear-common.h

/*
 * (C) Copyright 2009
 * Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SPEAR_COMMON_H
#define _SPEAR_COMMON_H
/*
 * Common configurations used for both spear3xx as well as spear6xx
 */

/* U-Boot Load Address */

/* Ethernet driver configuration */
#define CONFIG_MII
#define CONFIG_PHY_RESET_DELAY			10000		/* in usec */

/* USBD driver configuration */
#if defined(CONFIG_SPEAR_USBTTY)
#define CONFIG_DW_UDC
#define CONFIG_USB_DEVICE
#define CONFIG_USBD_HS
#define CONFIG_USB_TTY

#define CONFIG_USBD_PRODUCT_NAME		"SPEAr SoC"
#define CONFIG_USBD_MANUFACTURER		"ST Microelectronics"

#endif

#define CONFIG_EXTRA_ENV_USBTTY			"usbtty=cdc_acm\0"

/* I2C driver configuration */
#define CONFIG_SYS_I2C
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE			0xD0200000
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_I2C_BASE			0xD0180000
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_I2C_BASE			0xD0180000
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_I2C_BASE			0xD0180000
#endif
#define CONFIG_SYS_I2C_SPEED			400000
#define CONFIG_SYS_I2C_SLAVE			0x02

#define CONFIG_I2C_CHIPADDRESS			0x50

/* Timer, HZ specific defines */

/* Flash configuration */
#if defined(CONFIG_FLASH_PNOR)
#define CONFIG_SPEAR_EMI
#else
#define CONFIG_ST_SMI
#endif

#if defined(CONFIG_ST_SMI)

#define CONFIG_SYS_MAX_FLASH_BANKS		2
#define CONFIG_SYS_FLASH_BASE			0xF8000000
#define CONFIG_SYS_CS1_FLASH_BASE		0xF9000000
#define CONFIG_SYS_FLASH_BANK_SIZE		0x01000000
#define CONFIG_SYS_FLASH_ADDR_BASE		{CONFIG_SYS_FLASH_BASE, \
						CONFIG_SYS_CS1_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_SECT		128

#define CONFIG_SYS_FLASH_ERASE_TOUT		(3 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT		(3 * CONFIG_SYS_HZ)

#endif

/*
 * Serial Configuration (PL011)
 * CONFIG_PL01x_PORTS is defined in specific files
 */
#define CONFIG_PL011_CLOCK			(48 * 1000 * 1000)
#define CONFIG_CONS_INDEX			0
#define CONFIG_SYS_BAUDRATE_TABLE		{ 9600, 19200, 38400, \
						57600, 115200 }

#define CONFIG_SYS_LOADS_BAUD_CHANGE

/* NAND FLASH Configuration */
#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_NAND_FSMC
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_ONFI_DETECTION

/*
 * Default Environment Varible definitions
 */
#define CONFIG_ENV_OVERWRITE

/*
 * U-Boot Environment placing definitions.
 */
#if defined(CONFIG_ENV_IS_IN_FLASH)
#ifdef CONFIG_ST_SMI
/*
 * Environment is in serial NOR flash
 */
#define CONFIG_SYS_MONITOR_LEN			0x00040000
#define CONFIG_ENV_SECT_SIZE			0x00010000
#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "

#define CONFIG_BOOTCOMMAND			"bootm 0xf8050000"

#elif defined(CONFIG_SPEAR_EMI)
/*
 * Environment is in parallel NOR flash
 */
#define CONFIG_SYS_MONITOR_LEN			0x00060000
#define CONFIG_ENV_SECT_SIZE			0x00020000
#define CONFIG_FSMTDBLK				"/dev/mtdblock3 "

#define CONFIG_BOOTCOMMAND			"cp.b 0x50080000 0x1600000 " \
						"0x4C0000; bootm 0x1600000"
#endif

#define CONFIG_ENV_ADDR				(CONFIG_SYS_FLASH_BASE + \
						CONFIG_SYS_MONITOR_LEN)
#elif defined(CONFIG_ENV_IS_IN_NAND)
/*
 * Environment is in NAND
 */

#define CONFIG_ENV_OFFSET			0x60000
#define CONFIG_ENV_RANGE			0x10000
#define CONFIG_FSMTDBLK				"/dev/mtdblock7 "

#define CONFIG_BOOTCOMMAND			"nand read.jffs2 0x1600000 " \
						"0x80000 0x4C0000; " \
						"bootm 0x1600000"
#endif

#define CONFIG_NFSBOOTCOMMAND						\
	"bootp; "							\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$(serverip):$(rootpath) "				\
	"ip=$(ipaddr):$(serverip):$(gatewayip):"			\
			"$(netmask):$(hostname):$(netdev):off "		\
			"console=ttyAMA0,115200 $(othbootargs);"	\
	"bootm; "

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=ttyAMA0,115200 $(othbootargs);"		\
	CONFIG_BOOTCOMMAND

#define CONFIG_ENV_SIZE				0x02000
#define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE

/* Miscellaneous configurable options */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_BOOT_PARAMS_ADDR			0x00000100
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_MEMTEST_START		0x00800000
#define CONFIG_SYS_MEMTEST_END			0x04000000
#define CONFIG_SYS_MALLOC_LEN			(1024*1024)
#define CONFIG_SYS_LOAD_ADDR			0x00800000

#define CONFIG_SYS_FLASH_EMPTY_INFO

/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS			1
#define PHYS_SDRAM_1				0x00000000
#define PHYS_SDRAM_1_MAXSIZE			0x40000000

#define CONFIG_SYS_SDRAM_BASE			PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR		0xD2800000
#define CONFIG_SYS_INIT_RAM_SIZE		0x2000

#define CONFIG_SYS_INIT_SP_OFFSET		\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#endif
Commit	Line	Data
566c9c16 VK	1	/*
	2	* (C) Copyright 2009
	3	* Vipin Kumar, STMicroelectronics, <vipin.kumar@st.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
566c9c16 VK	6	*/
	7
	8	#ifndef _SPEAR_COMMON_H
	9	#define _SPEAR_COMMON_H
	10	/*
	11	* Common configurations used for both spear3xx as well as spear6xx
	12	*/
	13
a187559e	14	/* U-Boot Load Address */
f273e5b2	15
deb00562 VK	16	/* Ethernet driver configuration */
deb00562 VK	17	#define CONFIG_MII
deb00562 VK	18	#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
deb00562 VK	19
566c9c16	20	/* USBD driver configuration */
b884236e	21	#if defined(CONFIG_SPEAR_USBTTY)
2721551a	22	#define CONFIG_DW_UDC
566c9c16	23	#define CONFIG_USB_DEVICE
50726684	24	#define CONFIG_USBD_HS
566c9c16 VK	25	#define CONFIG_USB_TTY
	26
	27	#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC"
	28	#define CONFIG_USBD_MANUFACTURER "ST Microelectronics"
	29
b884236e VK	30	#endif
b884236e VK	31
566c9c16 VK	32	#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0"
	33
	34	/* I2C driver configuration */
678398b1	35	#define CONFIG_SYS_I2C
f93f589c AB	36	#if defined(CONFIG_SPEAR600)
	37	#define CONFIG_SYS_I2C_BASE 0xD0200000
	38	#elif defined(CONFIG_SPEAR300)
	39	#define CONFIG_SYS_I2C_BASE 0xD0180000
	40	#elif defined(CONFIG_SPEAR310)
	41	#define CONFIG_SYS_I2C_BASE 0xD0180000
	42	#elif defined(CONFIG_SPEAR320)
	43	#define CONFIG_SYS_I2C_BASE 0xD0180000
	44	#endif
566c9c16 VK	45	#define CONFIG_SYS_I2C_SPEED 400000
	46	#define CONFIG_SYS_I2C_SLAVE 0x02
	47
	48	#define CONFIG_I2C_CHIPADDRESS 0x50
	49
	50	/* Timer, HZ specific defines */
566c9c16 VK	51
	52	/* Flash configuration */
	53	#if defined(CONFIG_FLASH_PNOR)
9b382b43	54	#define CONFIG_SPEAR_EMI
566c9c16	55	#else
f3fcf92d	56	#define CONFIG_ST_SMI
566c9c16 VK	57	#endif
566c9c16 VK	58
f3fcf92d	59	#if defined(CONFIG_ST_SMI)
566c9c16 VK	60
566c9c16 VK	61	#define CONFIG_SYS_MAX_FLASH_BANKS 2
bc0bdf4c AV	62	#define CONFIG_SYS_FLASH_BASE 0xF8000000
	63	#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000
	64	#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
566c9c16 VK	65	#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \
	66	CONFIG_SYS_CS1_FLASH_BASE}
	67	#define CONFIG_SYS_MAX_FLASH_SECT 128
	68
566c9c16 VK	69	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
	70	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
	71
	72	#endif
	73
	74	/*
	75	* Serial Configuration (PL011)
	76	* CONFIG_PL01x_PORTS is defined in specific files
	77	*/
566c9c16 VK	78	#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
566c9c16 VK	79	#define CONFIG_CONS_INDEX 0
566c9c16 VK	80	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
	81	57600, 115200 }
	82
	83	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	84
	85	/* NAND FLASH Configuration */
1fa943b9	86	#define CONFIG_SYS_NAND_SELF_INIT
a39fcfb2 SH	87	#define CONFIG_MTD_DEVICE
a39fcfb2 SH	88	#define CONFIG_MTD_PARTITIONS
1fa943b9	89	#define CONFIG_NAND_FSMC
566c9c16	90	#define CONFIG_SYS_MAX_NAND_DEVICE 1
bc912e78	91	#define CONFIG_SYS_NAND_ONFI_DETECTION
566c9c16	92
566c9c16 VK	93	/*
	94	* Default Environment Varible definitions
	95	*/
566c9c16 VK	96	#define CONFIG_ENV_OVERWRITE
	97
	98	/*
	99	* U-Boot Environment placing definitions.
	100	*/
	101	#if defined(CONFIG_ENV_IS_IN_FLASH)
f3fcf92d	102	#ifdef CONFIG_ST_SMI
566c9c16 VK	103	/*
	104	* Environment is in serial NOR flash
	105	*/
	106	#define CONFIG_SYS_MONITOR_LEN 0x00040000
	107	#define CONFIG_ENV_SECT_SIZE 0x00010000
1b7935cd	108	#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
566c9c16 VK	109
	110	#define CONFIG_BOOTCOMMAND "bootm 0xf8050000"
	111
	112	#elif defined(CONFIG_SPEAR_EMI)
	113	/*
	114	* Environment is in parallel NOR flash
	115	*/
	116	#define CONFIG_SYS_MONITOR_LEN 0x00060000
	117	#define CONFIG_ENV_SECT_SIZE 0x00020000
	118	#define CONFIG_FSMTDBLK "/dev/mtdblock3 "
	119
	120	#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \
	121	"0x4C0000; bootm 0x1600000"
	122	#endif
	123
0296f159	124	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
566c9c16 VK	125	CONFIG_SYS_MONITOR_LEN)
	126	#elif defined(CONFIG_ENV_IS_IN_NAND)
	127	/*
	128	* Environment is in NAND
	129	*/
	130
	131	#define CONFIG_ENV_OFFSET 0x60000
	132	#define CONFIG_ENV_RANGE 0x10000
1b7935cd	133	#define CONFIG_FSMTDBLK "/dev/mtdblock7 "
566c9c16 VK	134
	135	#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \
	136	"0x80000 0x4C0000; " \
	137	"bootm 0x1600000"
	138	#endif
	139
1b7935cd VK	140	#define CONFIG_NFSBOOTCOMMAND \
	141	"bootp; " \
	142	"setenv bootargs root=/dev/nfs rw " \
	143	"nfsroot=$(serverip):$(rootpath) " \
	144	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	145	"$(netmask):$(hostname):$(netdev):off " \
	146	"console=ttyAMA0,115200 $(othbootargs);" \
	147	"bootm; "
	148
	149	#define CONFIG_RAMBOOTCOMMAND \
	150	"setenv bootargs root=/dev/ram rw " \
	151	"console=ttyAMA0,115200 $(othbootargs);" \
	152	CONFIG_BOOTCOMMAND
	153
566c9c16	154	#define CONFIG_ENV_SIZE 0x02000
0296f159	155	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
566c9c16 VK	156
566c9c16 VK	157	/* Miscellaneous configurable options */
962d026b	158	#define CONFIG_ARCH_CPU_INIT
566c9c16	159	#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
9b382b43 AV	160	#define CONFIG_CMDLINE_TAG
	161	#define CONFIG_SETUP_MEMORY_TAGS
	162	#define CONFIG_MISC_INIT_R
566c9c16 VK	163
	164	#define CONFIG_SYS_MEMTEST_START 0x00800000
	165	#define CONFIG_SYS_MEMTEST_END 0x04000000
	166	#define CONFIG_SYS_MALLOC_LEN (1024*1024)
566c9c16	167	#define CONFIG_SYS_LOAD_ADDR 0x00800000
566c9c16	168
cc4b5a34 VK	169	#define CONFIG_SYS_FLASH_EMPTY_INFO
cc4b5a34 VK	170
566c9c16 VK	171	/* Physical Memory Map */
	172	#define CONFIG_NR_DRAM_BANKS 1
	173	#define PHYS_SDRAM_1 0x00000000
	174	#define PHYS_SDRAM_1_MAXSIZE 0x40000000
	175
a39fcfb2 SH	176	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	177	#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000
	178	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
	179
	180	#define CONFIG_SYS_INIT_SP_OFFSET \
	181	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	182
	183	#define CONFIG_SYS_INIT_SP_ADDR \
	184	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	185
566c9c16	186	#endif