[people/ms/u-boot.git] / include / configs / stm32f429-discovery.h

/*
 * (C) Copyright 2015
 * Kamil Lulko, <kamil.lulko@gmail.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_STM32F4DISCOVERY

#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_FLASH_BASE		0x08000000

#define CONFIG_SYS_INIT_SP_ADDR		0x10010000
#define CONFIG_SYS_TEXT_BASE		0x08000000

#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF

/*
 * Configuration of the external SDRAM memory
 */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_RAM_CS		1
#define CONFIG_SYS_RAM_FREQ_DIV		2
#define CONFIG_SYS_RAM_BASE		0xD0000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_LOAD_ADDR		0xD0400000
#define CONFIG_LOADADDR			0xD0400000

#define CONFIG_SYS_MAX_FLASH_SECT	12
#define CONFIG_SYS_MAX_FLASH_BANKS	2

#define CONFIG_ENV_OFFSET		(256 << 10)
#define CONFIG_ENV_SECT_SIZE		(128 << 10)
#define CONFIG_ENV_SIZE			(8 << 10)

#define CONFIG_RED_LED			110
#define CONFIG_GREEN_LED		109

#define CONFIG_STM32_FLASH

#define CONFIG_STM32_HSE_HZ		8000000

#define CONFIG_SYS_CLK_FREQ		180000000 /* 180 MHz */

#define CONFIG_SYS_HZ_CLOCK		1000000	/* Timer is clocked at 1MHz */

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

#define CONFIG_SYS_CBSIZE		1024

#define CONFIG_SYS_MALLOC_LEN		(2 << 20)

#define CONFIG_BOOTCOMMAND						\
	"run bootcmd_romfs"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
	"bootm 0x08044000 - 0x08042000\0"

/*
 * Command line configuration.
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING

#endif /* __CONFIG_H */
Commit	Line	Data
ed09a554	1	/*
ed09a554	2	* (C) Copyright 2015
66562414	3	* Kamil Lulko, <kamil.lulko@gmail.com>
ed09a554	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
ed09a554	11	#define CONFIG_STM32F4DISCOVERY
ed09a554	12
089fddfd	13	#define CONFIG_MISC_INIT_R
ed09a554	14
	15	#define CONFIG_SYS_FLASH_BASE 0x08000000
	16
	17	#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
	18	#define CONFIG_SYS_TEXT_BASE 0x08000000
	19
	20	#define CONFIG_SYS_ICACHE_OFF
	21	#define CONFIG_SYS_DCACHE_OFF
	22
	23	/*
	24	* Configuration of the external SDRAM memory
	25	*/
	26	#define CONFIG_NR_DRAM_BANKS 1
ed09a554	27	#define CONFIG_SYS_RAM_CS 1
	28	#define CONFIG_SYS_RAM_FREQ_DIV 2
	29	#define CONFIG_SYS_RAM_BASE 0xD0000000
	30	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
	31	#define CONFIG_SYS_LOAD_ADDR 0xD0400000
	32	#define CONFIG_LOADADDR 0xD0400000
	33
	34	#define CONFIG_SYS_MAX_FLASH_SECT 12
	35	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	36
ed09a554	37	#define CONFIG_ENV_OFFSET (256 << 10)
	38	#define CONFIG_ENV_SECT_SIZE (128 << 10)
	39	#define CONFIG_ENV_SIZE (8 << 10)
	40
ed09a554	41	#define CONFIG_RED_LED 110
	42	#define CONFIG_GREEN_LED 109
	43
9ecb0c41	44	#define CONFIG_STM32_FLASH
ed09a554	45
	46	#define CONFIG_STM32_HSE_HZ 8000000
	47
f9fa4a25 AB	48	#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
f9fa4a25 AB	49
ed09a554	50	#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
	51
	52	#define CONFIG_CMDLINE_TAG
	53	#define CONFIG_SETUP_MEMORY_TAGS
	54	#define CONFIG_INITRD_TAG
	55	#define CONFIG_REVISION_TAG
	56
	57	#define CONFIG_SYS_CBSIZE 1024
ed09a554	58
ed09a554	59	#define CONFIG_SYS_MALLOC_LEN (2 << 20)
ed09a554	60
ed09a554	61	#define CONFIG_BOOTCOMMAND \
	62	"run bootcmd_romfs"
	63
	64	#define CONFIG_EXTRA_ENV_SETTINGS \
	65	"bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \
	66	"bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \
	67	"bootm 0x08044000 - 0x08042000\0"
	68
ed09a554	69	/*
	70	* Command line configuration.
	71	*/
ed09a554	72	#define CONFIG_SYS_LONGHELP
ed09a554	73	#define CONFIG_AUTO_COMPLETE
	74	#define CONFIG_CMDLINE_EDITING
	75
ed09a554	76	#endif /* __CONFIG_H */