[people/ms/u-boot.git] / include / configs / strider.h

/*
 * (C) Copyright 2014
 * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
 *
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC83xx		1 /* MPC83xx family */
#define CONFIG_MPC830x		1 /* MPC830x family */
#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
#define CONFIG_STRIDER		1 /* STRIDER board specific */

#define	CONFIG_SYS_TEXT_BASE	0xFE000000

#ifdef CONFIG_STRIDER_CPU
#define CONFIG_IDENT_STRING	" strider cpu 0.01"
#else
#define CONFIG_IDENT_STRING	" strider con 0.01"
#endif

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT

#define CONFIG_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111

#define CONFIG_CMD_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2

#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_CMD_FPGAD
#define CONFIG_CMD_IOLOOP

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

/*
 * Hardware Reset Configuration Word
 * if CLKIN is 66.66MHz, then
 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
 * We choose the A type silicon as default, so the core is 400Mhz.
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_SVCOD_DIV_2 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_CORE_TO_CSB_3X1)
/*
 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
 * in 8308's HRCWH according to the manual, but original Freescale's
 * code has them and I've expirienced some problems using the board
 * with BDI3000 attached when I've tried to set these bits to zero
 * (UART doesn't work after the 'reset run' command).
 */
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0XFFF00100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_MII |\
	HRCWH_TSEC2M_IN_RGMII |\
	HRCWH_BIG_ENDIAN)

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH (\
	SICRH_ESDHC_A_SD |\
	SICRH_ESDHC_B_SD |\
	SICRH_ESDHC_C_SD |\
	SICRH_GPIO_A_GPIO |\
	SICRH_GPIO_B_GPIO |\
	SICRH_IEEE1588_A_GPIO |\
	SICRH_USB |\
	SICRH_GTM_GPIO |\
	SICRH_IEEE1588_B_GPIO |\
	SICRH_ETSEC2_GPIO |\
	SICRH_GPIOSEL_1 |\
	SICRH_TMROBI_V3P3 |\
	SICRH_TSOBI1_V2P5 |\
	SICRH_TSOBI2_V2P5)	/* 0x0037f103 */
#define CONFIG_SYS_SICRL (\
	SICRL_SPI_PF0 |\
	SICRL_UART_PF0 |\
	SICRL_IRQ_PF0 |\
	SICRL_I2C2_PF0 |\
	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of one chip NT5TU64M16HG from NANYA
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ODT_RD_NEVER \
				| CSCONFIG_ODT_WR_ONLY_CURRENT \
				| CSCONFIG_BANK_BIT_3 \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00260802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
				| (9 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26279222 */
#define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x021848c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x08240100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_DBW_16)
				/* 0x43100000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0440 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0242 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=4, AL=0 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000

/*
 * FLASH on the Local Bus
 */
#if 1
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
#else
#define CONFIG_SYS_NO_FLASH
#endif

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */

/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * FPGA
 */
#define CONFIG_SYS_FPGA0_BASE		0xE0600000
#define CONFIG_SYS_FPGA0_SIZE		1 /* FPGA size is 1M */

/* Window base at FPGA base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_1MB)

#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FPGA0_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */

#define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_SCY_5 \
				| OR_GPCM_TRLX_CLEAR \
				| OR_GPCM_EHTR_CLEAR)

#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
#define CONFIG_SYS_FPGA_DONE(k)		0x0010

#define CONFIG_SYS_FPGA_COUNT		1

#define CONFIG_SYS_MCLINK_MAX		3

#define CONFIG_SYS_FPGA_PTR \
	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }

#define CONFIG_SYS_FPGA_NO_RFL_HI

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* Pass open firmware flat tree */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000

#define CONFIG_PCA953X			/* NXP PCA9554 */
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_SYS_I2C_PCA953X_WIDTH    { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
					  {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }

#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
#define CONFIG_SYS_I2C_IHS_CH1
#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
#define CONFIG_SYS_I2C_IHS_CH2
#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
#define CONFIG_SYS_I2C_IHS_CH3
#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F

/*
 * Software (bit-bang) I2C driver configuration
 */
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_SOFT_SPEED		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE		0x7F
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_2		0x7F
#define I2C_SOFT_DECLARATIONS3
#define CONFIG_SYS_I2C_SOFT_SPEED_3		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_3		0x7F
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
#ifdef CONFIG_STRIDER_CON
#define I2C_SOFT_DECLARATIONS5
#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
#define I2C_SOFT_DECLARATIONS6
#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
#define I2C_SOFT_DECLARATIONS7
#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
#define I2C_SOFT_DECLARATIONS8
#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
#endif

#ifdef CONFIG_STRIDER_CON
#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
#define CONFIG_SYS_ADV7611_I2C			{5, 6, 7, 8}
#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
#define CONFIG_STRIDER_FANS			{ {10, 0x4c}, {11, 0x4c}, \
						  {12, 0x4c} }
#else
#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
#define CONFIG_SYS_ADV7611_I2C			{1, 2, 3, 4}
#define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
#define CONFIG_STRIDER_FANS			{ {2, 0x18}, {3, 0x18}, \
						  {4, 0x18} }
#endif

#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
#endif

#ifdef CONFIG_STRIDER_CON
#define I2C_SDA_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
#define I2C_SCL_GPIO	((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
#define I2C_FPGA_IDX	((I2C_ADAP_HWNR > 3) ? \
			 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
#else
#define I2C_SDA_GPIO	0x0040
#define I2C_SCL_GPIO	0x0020
#define I2C_FPGA_IDX	I2C_ADAP_HWNR
#endif
#define I2C_ACTIVE	{ }
#define I2C_TRISTATE	{ }
#define I2C_READ \
	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
#define I2C_SDA(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
		else \
			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
	} while (0)
#define I2C_SCL(bit) \
	do { \
		if (bit) \
			fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
		else \
			fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
	} while (0)
#define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */

/*
 * Software (bit-bang) MII driver configuration
 */
#define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
#define CONFIG_BITBANGMII_MULTI

/*
 * OSD Setup
 */
#define CONFIG_SYS_OSD_SCREENS		1
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE

#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_MII		1 /* MII PHY management */
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define TSEC1_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC1_FLAGS		0

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#if 1
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
#else
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * Command line configuration.
 */
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */

#undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

#define CONFIG_SYS_CONSOLE_INFO_QUIET

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_RW | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
					BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
					BATL_CACHEINHIBIT | \
					BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */

#define CONFIG_HOSTNAME		hrcon
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_PREBOOT		/* enable preboot variable */

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS1\0"						\
	"u-boot=u-boot.bin\0"						\
	"kernel_addr=1000000\0"					\
	"fdt_addr=C00000\0"						\
	"fdtfile=hrcon.dtb\0"				\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
		" +${filesize};cp.b ${fileaddr} "			\
		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
	"upd=run load update\0"						\

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp ${kernel_addr} $bootfile;"				\
	"tftp ${fdt_addr} $fdtfile;"					\
	"bootm ${kernel_addr} - ${fdt_addr}"

#define CONFIG_MMCBOOTCOMMAND						\
	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait "		\
	"console=$consoledev,$baudrate $othbootargs;"			\
	"ext2load mmc 0:2 ${kernel_addr} $bootfile;"			\
	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;"			\
	"bootm ${kernel_addr} - ${fdt_addr}"

#define CONFIG_BOOTCOMMAND		CONFIG_MMCBOOTCOMMAND


#endif	/* __CONFIG_H */
Commit	Line	Data
a3f9d6c7 DE	1	/*
	2	* (C) Copyright 2014
	3	* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
	4	*
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
	12	/*
	13	* High Level Configuration Options
	14	*/
	15	#define CONFIG_E300 1 /* E300 family */
	16	#define CONFIG_MPC83xx 1 /* MPC83xx family */
	17	#define CONFIG_MPC830x 1 /* MPC830x family */
	18	#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
	19	#define CONFIG_STRIDER 1 /* STRIDER board specific */
	20
	21	#define CONFIG_SYS_TEXT_BASE 0xFE000000
	22
	23	#ifdef CONFIG_STRIDER_CPU
	24	#define CONFIG_IDENT_STRING " strider cpu 0.01"
	25	#else
	26	#define CONFIG_IDENT_STRING " strider con 0.01"
	27	#endif
	28
	29	#define CONFIG_BOARD_EARLY_INIT_F
	30	#define CONFIG_BOARD_EARLY_INIT_R
	31	#define CONFIG_LAST_STAGE_INIT
	32
a3f9d6c7 DE	33	#define CONFIG_MMC
	34	#define CONFIG_FSL_ESDHC
	35	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
	36	#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
	37
	38	#define CONFIG_CMD_MMC
	39	#define CONFIG_GENERIC_MMC
	40	#define CONFIG_DOS_PARTITION
	41	#define CONFIG_CMD_EXT2
	42
	43	#define CONFIG_CMD_MEMTEST
	44	#define CONFIG_SYS_ALT_MEMTEST
	45
	46	#define CONFIG_CMD_FPGAD
	47	#define CONFIG_CMD_IOLOOP
	48
	49	/*
	50	* System Clock Setup
	51	*/
	52	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	53	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	54
	55	/*
	56	* Hardware Reset Configuration Word
	57	* if CLKIN is 66.66MHz, then
	58	* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
	59	* We choose the A type silicon as default, so the core is 400Mhz.
	60	*/
	61	#define CONFIG_SYS_HRCW_LOW (\
	62	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	63	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	64	HRCWL_SVCOD_DIV_2 \|\
	65	HRCWL_CSB_TO_CLKIN_4X1 \|\
	66	HRCWL_CORE_TO_CSB_3X1)
	67	/*
	68	* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
	69	* in 8308's HRCWH according to the manual, but original Freescale's
	70	* code has them and I've expirienced some problems using the board
	71	* with BDI3000 attached when I've tried to set these bits to zero
	72	* (UART doesn't work after the 'reset run' command).
	73	*/
	74	#define CONFIG_SYS_HRCW_HIGH (\
	75	HRCWH_PCI_HOST \|\
	76	HRCWH_PCI1_ARBITER_ENABLE \|\
	77	HRCWH_CORE_ENABLE \|\
	78	HRCWH_FROM_0XFFF00100 \|\
	79	HRCWH_BOOTSEQ_DISABLE \|\
	80	HRCWH_SW_WATCHDOG_DISABLE \|\
	81	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	82	HRCWH_RL_EXT_LEGACY \|\
	83	HRCWH_TSEC1M_IN_MII \|\
	84	HRCWH_TSEC2M_IN_RGMII \|\
	85	HRCWH_BIG_ENDIAN)
	86
	87	/*
	88	* System IO Config
	89	*/
	90	#define CONFIG_SYS_SICRH (\
	91	SICRH_ESDHC_A_SD \|\
	92	SICRH_ESDHC_B_SD \|\
	93	SICRH_ESDHC_C_SD \|\
	94	SICRH_GPIO_A_GPIO \|\
	95	SICRH_GPIO_B_GPIO \|\
	96	SICRH_IEEE1588_A_GPIO \|\
97	SICRH_USB \|\
98	SICRH_GTM_GPIO \|\
99	SICRH_IEEE1588_B_GPIO \|\
100	SICRH_ETSEC2_GPIO \|\
101	SICRH_GPIOSEL_1 \|\
102	SICRH_TMROBI_V3P3 \|\
103	SICRH_TSOBI1_V2P5 \|\
104	SICRH_TSOBI2_V2P5) /* 0x0037f103 */
105	#define CONFIG_SYS_SICRL (\
106	SICRL_SPI_PF0 \|\
107	SICRL_UART_PF0 \|\
108	SICRL_IRQ_PF0 \|\
109	SICRL_I2C2_PF0 \|\
110	SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
111
112	/*
113	* IMMR new address
114	*/
115	#define CONFIG_SYS_IMMR 0xE0000000
116
117	/*
118	* SERDES
119	*/
120	#define CONFIG_FSL_SERDES
121	#define CONFIG_FSL_SERDES1 0xe3000
122
123	/*
124	* Arbiter Setup
125	*/
126	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
127	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
128	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
129
130	/*
131	* DDR Setup
132	*/
133	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
134	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
135	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
136	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
137	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
138	\| DDRCDR_PZ_LOZ \
139	\| DDRCDR_NZ_LOZ \
140	\| DDRCDR_ODT \
141	\| DDRCDR_Q_DRN)
142	/* 0x7b880001 */
143	/*
144	* Manually set up DDR parameters
145	* consist of one chip NT5TU64M16HG from NANYA
146	*/
147
148	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
149
150	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
151	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
152	\| CSCONFIG_ODT_RD_NEVER \
153	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
154	\| CSCONFIG_BANK_BIT_3 \
155	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10)
156	/* 0x80010102 */
157	#define CONFIG_SYS_DDR_TIMING_3 0
158	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
159	\| (0 << TIMING_CFG0_WRT_SHIFT) \
160	\| (0 << TIMING_CFG0_RRT_SHIFT) \
161	\| (0 << TIMING_CFG0_WWT_SHIFT) \
162	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
163	\| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
164	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
165	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
166	/* 0x00260802 */
167	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
168	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
169	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
170	\| (7 << TIMING_CFG1_CASLAT_SHIFT) \
171	\| (9 << TIMING_CFG1_REFREC_SHIFT) \
172	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
173	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
174	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
175	/* 0x26279222 */
176	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
177	\| (4 << TIMING_CFG2_CPO_SHIFT) \
178	\| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
179	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
180	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
181	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
182	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
183	/* 0x021848c5 */
184	#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
185	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
186	/* 0x08240100 */
187	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
188	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
189	\| SDRAM_CFG_DBW_16)
190	/* 0x43100000 */
191
192	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
193	#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
194	\| (0x0242 << SDRAM_MODE_SD_SHIFT))
195	/* ODT 150ohm CL=4, AL=0 on SDRAM */
196	#define CONFIG_SYS_DDR_MODE2 0x00000000
197
198	/*
199	* Memory test
200	*/
201	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
202	#define CONFIG_SYS_MEMTEST_END 0x07f00000
203
204	/*
205	* The reserved memory
206	*/
207	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
208
209	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
210	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
211
212	/*
213	* Initial RAM Base Address Setup
214	*/
215	#define CONFIG_SYS_INIT_RAM_LOCK 1
216	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
217	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
218	#define CONFIG_SYS_GBL_DATA_OFFSET \
219	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
220
221	/*
222	* Local Bus Configuration & Clock Setup
223	*/
224	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
225	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
226	#define CONFIG_SYS_LBC_LBCR 0x00040000
227
228	/*
229	* FLASH on the Local Bus
230	*/
231	#if 1
232	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
233	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
234	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
235	#define CONFIG_FLASH_CFI_LEGACY
236	#define CONFIG_SYS_FLASH_LEGACY_512Kx16
237	#else
238	#define CONFIG_SYS_NO_FLASH
239	#endif
240
241	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
242	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
243	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
244
245	/* Window base at flash base */
246	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
247	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
248
249	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
250	\| BR_PS_16 /* 16 bit port */ \
251	\| BR_MS_GPCM /* MSEL = GPCM */ \
252	\| BR_V) /* valid */
253	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
254	\| OR_UPM_XAM \
255	\| OR_GPCM_CSNT \
256	\| OR_GPCM_ACS_DIV2 \
257	\| OR_GPCM_XACS \
258	\| OR_GPCM_SCY_15 \
259	\| OR_GPCM_TRLX_SET \
260	\| OR_GPCM_EHTR_SET)
261
262	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
263	#define CONFIG_SYS_MAX_FLASH_SECT 135
264
265	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
266	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
267
268	/*
269	* FPGA
270	*/
271	#define CONFIG_SYS_FPGA0_BASE 0xE0600000
272	#define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */
273
274	/* Window base at FPGA base */
275	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE
276	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_1MB)
277
278	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \
279	\| BR_PS_16 /* 16 bit port */ \
280	\| BR_MS_GPCM /* MSEL = GPCM */ \
281	\| BR_V) /* valid */
a119357c RP	282
a119357c RP	283	#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \
a3f9d6c7 DE	284	\| OR_UPM_XAM \
a3f9d6c7 DE	285	\| OR_GPCM_CSNT \
a119357c RP	286	\| OR_GPCM_SCY_5 \
	287	\| OR_GPCM_TRLX_CLEAR \
	288	\| OR_GPCM_EHTR_CLEAR)
a3f9d6c7 DE	289
	290	#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
	291	#define CONFIG_SYS_FPGA_DONE(k) 0x0010
	292
	293	#define CONFIG_SYS_FPGA_COUNT 1
	294
	295	#define CONFIG_SYS_MCLINK_MAX 3
	296
	297	#define CONFIG_SYS_FPGA_PTR \
	298	{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
	299
	300	#define CONFIG_SYS_FPGA_NO_RFL_HI
	301
	302	/*
	303	* Serial Port
	304	*/
	305	#define CONFIG_CONS_INDEX 2
a3f9d6c7 DE	306	#define CONFIG_SYS_NS16550_SERIAL
	307	#define CONFIG_SYS_NS16550_REG_SIZE 1
	308	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	309
	310	#define CONFIG_SYS_BAUDRATE_TABLE \
	311	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	312
	313	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	314	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	315
a3f9d6c7	316	/* Pass open firmware flat tree */
a3f9d6c7 DE	317
	318	/* I2C */
	319	#define CONFIG_SYS_I2C
	320	#define CONFIG_SYS_I2C_FSL
	321	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	322	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	323	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	324
	325	#define CONFIG_PCA953X /* NXP PCA9554 */
47098056 DE	326	#define CONFIG_CMD_PCA953X
	327	#define CONFIG_CMD_PCA953X_INFO
	328	#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
	329	{0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
	330
a3f9d6c7 DE	331	#define CONFIG_PCA9698 /* NXP PCA9698 */
	332
	333	#define CONFIG_SYS_I2C_IHS
	334	#define CONFIG_SYS_I2C_IHS_CH0
	335	#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
	336	#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
	337	#define CONFIG_SYS_I2C_IHS_CH1
	338	#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
	339	#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
	340	#define CONFIG_SYS_I2C_IHS_CH2
	341	#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
	342	#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
	343	#define CONFIG_SYS_I2C_IHS_CH3
	344	#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
	345	#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
	346
	347	/*
	348	* Software (bit-bang) I2C driver configuration
	349	*/
	350	#define CONFIG_SYS_I2C_SOFT
	351	#define CONFIG_SOFT_I2C_READ_REPEATED_START
	352	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	353	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
	354	#define I2C_SOFT_DECLARATIONS2
	355	#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
	356	#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
	357	#define I2C_SOFT_DECLARATIONS3
	358	#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
	359	#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
	360	#define I2C_SOFT_DECLARATIONS4
	361	#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
	362	#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
	363	#ifdef CONFIG_STRIDER_CON
	364	#define I2C_SOFT_DECLARATIONS5
	365	#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
	366	#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
	367	#define I2C_SOFT_DECLARATIONS6
	368	#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
	369	#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
	370	#define I2C_SOFT_DECLARATIONS7
	371	#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
	372	#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
	373	#define I2C_SOFT_DECLARATIONS8
	374	#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
	375	#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
	376	#endif
	377
	378	#ifdef CONFIG_STRIDER_CON
	379	#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
	380	#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
	381	#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
	382	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
	383	#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
	384	{12, 0x4c} }
	385	#else
	386	#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
	387	#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
	388	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
	389	#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
	390	{4, 0x18} }
	391	#endif
	392
	393	#ifndef __ASSEMBLY__
	394	void fpga_gpio_set(unsigned int bus, int pin);
395	void fpga_gpio_clear(unsigned int bus, int pin);
396	int fpga_gpio_get(unsigned int bus, int pin);
397	#endif
398
399	#ifdef CONFIG_STRIDER_CON
400	#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
401	#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
402	#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
403	(I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
404	#else
405	#define I2C_SDA_GPIO 0x0040
406	#define I2C_SCL_GPIO 0x0020
407	#define I2C_FPGA_IDX I2C_ADAP_HWNR
408	#endif
409	#define I2C_ACTIVE { }
410	#define I2C_TRISTATE { }
411	#define I2C_READ \
412	(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
413	#define I2C_SDA(bit) \
414	do { \
415	if (bit) \
416	fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
417	else \
418	fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
419	} while (0)
420	#define I2C_SCL(bit) \
421	do { \
422	if (bit) \
423	fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
424	else \
425	fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
426	} while (0)
427	#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
428
429	/*
430	* Software (bit-bang) MII driver configuration
431	*/
432	#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
433	#define CONFIG_BITBANGMII_MULTI
434
435	/*
436	* OSD Setup
437	*/
438	#define CONFIG_SYS_OSD_SCREENS 1
439	#define CONFIG_SYS_DP501_DIFFERENTIAL
440	#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
441
442	/*
443	* General PCI
444	* Addresses are mapped 1-1.
445	*/
446	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
447	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
448	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
449	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
450	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
451	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
452	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
453	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
454	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
455
456	/* enable PCIE clock */
457	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
458
459	#define CONFIG_PCI
460	#define CONFIG_PCI_INDIRECT_BRIDGE
461	#define CONFIG_PCIE
462
463	#define CONFIG_PCI_PNP /* do pci plug-and-play */
464
465	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
466	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
467
468	/*
469	* TSEC
470	*/
471	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
472	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
473	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
474
475	/*
476	* TSEC ethernet configuration
477	*/
478	#define CONFIG_MII 1 /* MII PHY management */
479	#define CONFIG_TSEC1
480	#define CONFIG_TSEC1_NAME "eTSEC0"
481	#define TSEC1_PHY_ADDR 1
482	#define TSEC1_PHYIDX 0
483	#define TSEC1_FLAGS 0
484
485	/* Options are: eTSEC[0-1] */
486	#define CONFIG_ETHPRIME "eTSEC0"
487
488	/*
489	* Environment
490	*/
491	#if 1
492	#define CONFIG_ENV_IS_IN_FLASH 1
493	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
494	CONFIG_SYS_MONITOR_LEN)
495	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
496	#define CONFIG_ENV_SIZE 0x2000
497	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
498	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
499	#else
500	#define CONFIG_ENV_IS_NOWHERE
501	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
502	#endif
503
504	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
505	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
506
507	/*
508	* Command line configuration.
509	*/
510	#define CONFIG_CMD_I2C
511	#define CONFIG_CMD_MII
512	#define CONFIG_CMD_PCI
513	#define CONFIG_CMD_PING
514
515	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
516	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
517
518	/*
519	* Miscellaneous configurable options
520	*/
521	#define CONFIG_SYS_LONGHELP /* undef to save memory */
522	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
523	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
524
525	#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
526
527	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
528
529	#define CONFIG_SYS_CONSOLE_INFO_QUIET
530
531	/* Print Buffer Size */
532	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
533	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
534	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
535
536	/*
537	* For booting Linux, the board info and command line data
538	* have to be in the first 256 MB of memory, since this is
539	* the maximum mapped by the Linux kernel during initialization.
540	*/
541	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
542
543	/*
544	* Core HID Setup
545	*/
546	#define CONFIG_SYS_HID0_INIT 0x000000000
547	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
548	HID0_ENABLE_INSTRUCTION_CACHE \| \
549	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
550	#define CONFIG_SYS_HID2 HID2_HBE
551
552	/*
553	* MMU Setup
554	*/
555
556	/* DDR: cache cacheable */
557	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_RW \| \
558	BATL_MEMCOHERENCE)
559	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_128M \| \
560	BATU_VS \| BATU_VP)
561	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
562	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
563
564	/* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */
565	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_RW \| \
566	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
567	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \| BATU_BL_8M \| BATU_VS \| \
568	BATU_VP)
569	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
570	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
571
572	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
573	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
574	BATL_MEMCOHERENCE)
575	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \| BATU_BL_8M \| \
576	BATU_VS \| BATU_VP)
577	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_RW \| \
578	BATL_CACHEINHIBIT \| \
579	BATL_GUARDEDSTORAGE)
580	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
581
582	/* Stack in dcache: cacheable, no memory coherence */
583	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
584	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| \
585	BATU_VS \| BATU_VP)
586	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
587	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
588
589	/*
590	* Environment Configuration
591	*/
592
593	#define CONFIG_ENV_OVERWRITE
594
595	#if defined(CONFIG_TSEC_ENET)
596	#define CONFIG_HAS_ETH0
597	#endif
598
599	#define CONFIG_BAUDRATE 115200
600
601	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
602
603	#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
604
605	#define CONFIG_HOSTNAME hrcon
606	#define CONFIG_ROOTPATH "/opt/nfsroot"
607	#define CONFIG_BOOTFILE "uImage"
608
609	#define CONFIG_PREBOOT /* enable preboot variable */
610
611	#define CONFIG_EXTRA_ENV_SETTINGS \
612	"netdev=eth0\0" \
613	"consoledev=ttyS1\0" \
614	"u-boot=u-boot.bin\0" \
615	"kernel_addr=1000000\0" \
616	"fdt_addr=C00000\0" \
617	"fdtfile=hrcon.dtb\0" \
618	"load=tftp ${loadaddr} ${u-boot}\0" \
619	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
620	" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
621	" +${filesize};cp.b ${fileaddr} " \
622	__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
623	"upd=run load update\0" \
624
625	#define CONFIG_NFSBOOTCOMMAND \
626	"setenv bootargs root=/dev/nfs rw " \
627	"nfsroot=$serverip:$rootpath " \
628	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
629	"console=$consoledev,$baudrate $othbootargs;" \
630	"tftp ${kernel_addr} $bootfile;" \
631	"tftp ${fdt_addr} $fdtfile;" \
632	"bootm ${kernel_addr} - ${fdt_addr}"
633
634	#define CONFIG_MMCBOOTCOMMAND \
635	"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
636	"console=$consoledev,$baudrate $othbootargs;" \
637	"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
638	"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
639	"bootm ${kernel_addr} - ${fdt_addr}"
640
641	#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
642
643
644	#endif /* __CONFIG_H */