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a3f9d6c7 DE |
1 | /* |
2 | * (C) Copyright 2014 | |
3 | * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de | |
4 | * | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
12 | /* | |
13 | * High Level Configuration Options | |
14 | */ | |
15 | #define CONFIG_E300 1 /* E300 family */ | |
16 | #define CONFIG_MPC83xx 1 /* MPC83xx family */ | |
17 | #define CONFIG_MPC830x 1 /* MPC830x family */ | |
18 | #define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ | |
19 | #define CONFIG_STRIDER 1 /* STRIDER board specific */ | |
20 | ||
21 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 | |
22 | ||
a3f9d6c7 DE |
23 | #define CONFIG_BOARD_EARLY_INIT_F |
24 | #define CONFIG_BOARD_EARLY_INIT_R | |
25 | #define CONFIG_LAST_STAGE_INIT | |
26 | ||
a3f9d6c7 DE |
27 | #define CONFIG_MMC |
28 | #define CONFIG_FSL_ESDHC | |
29 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR | |
30 | #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 | |
31 | ||
a3f9d6c7 DE |
32 | #define CONFIG_GENERIC_MMC |
33 | #define CONFIG_DOS_PARTITION | |
a3f9d6c7 | 34 | |
a3f9d6c7 DE |
35 | #define CONFIG_SYS_ALT_MEMTEST |
36 | ||
37 | #define CONFIG_CMD_FPGAD | |
38 | #define CONFIG_CMD_IOLOOP | |
39 | ||
40 | /* | |
41 | * System Clock Setup | |
42 | */ | |
43 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
44 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
45 | ||
46 | /* | |
47 | * Hardware Reset Configuration Word | |
48 | * if CLKIN is 66.66MHz, then | |
49 | * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz | |
50 | * We choose the A type silicon as default, so the core is 400Mhz. | |
51 | */ | |
52 | #define CONFIG_SYS_HRCW_LOW (\ | |
53 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
54 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
55 | HRCWL_SVCOD_DIV_2 |\ | |
56 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
57 | HRCWL_CORE_TO_CSB_3X1) | |
58 | /* | |
59 | * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits | |
60 | * in 8308's HRCWH according to the manual, but original Freescale's | |
61 | * code has them and I've expirienced some problems using the board | |
62 | * with BDI3000 attached when I've tried to set these bits to zero | |
63 | * (UART doesn't work after the 'reset run' command). | |
64 | */ | |
65 | #define CONFIG_SYS_HRCW_HIGH (\ | |
66 | HRCWH_PCI_HOST |\ | |
67 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
68 | HRCWH_CORE_ENABLE |\ | |
69 | HRCWH_FROM_0XFFF00100 |\ | |
70 | HRCWH_BOOTSEQ_DISABLE |\ | |
71 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
72 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
73 | HRCWH_RL_EXT_LEGACY |\ | |
74 | HRCWH_TSEC1M_IN_MII |\ | |
75 | HRCWH_TSEC2M_IN_RGMII |\ | |
76 | HRCWH_BIG_ENDIAN) | |
77 | ||
78 | /* | |
79 | * System IO Config | |
80 | */ | |
81 | #define CONFIG_SYS_SICRH (\ | |
82 | SICRH_ESDHC_A_SD |\ | |
83 | SICRH_ESDHC_B_SD |\ | |
84 | SICRH_ESDHC_C_SD |\ | |
85 | SICRH_GPIO_A_GPIO |\ | |
86 | SICRH_GPIO_B_GPIO |\ | |
87 | SICRH_IEEE1588_A_GPIO |\ | |
88 | SICRH_USB |\ | |
89 | SICRH_GTM_GPIO |\ | |
90 | SICRH_IEEE1588_B_GPIO |\ | |
91 | SICRH_ETSEC2_GPIO |\ | |
92 | SICRH_GPIOSEL_1 |\ | |
93 | SICRH_TMROBI_V3P3 |\ | |
94 | SICRH_TSOBI1_V2P5 |\ | |
95 | SICRH_TSOBI2_V2P5) /* 0x0037f103 */ | |
96 | #define CONFIG_SYS_SICRL (\ | |
97 | SICRL_SPI_PF0 |\ | |
98 | SICRL_UART_PF0 |\ | |
99 | SICRL_IRQ_PF0 |\ | |
100 | SICRL_I2C2_PF0 |\ | |
101 | SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ | |
102 | ||
103 | /* | |
104 | * IMMR new address | |
105 | */ | |
106 | #define CONFIG_SYS_IMMR 0xE0000000 | |
107 | ||
108 | /* | |
109 | * SERDES | |
110 | */ | |
111 | #define CONFIG_FSL_SERDES | |
112 | #define CONFIG_FSL_SERDES1 0xe3000 | |
113 | ||
114 | /* | |
115 | * Arbiter Setup | |
116 | */ | |
117 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ | |
118 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ | |
119 | #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ | |
120 | ||
121 | /* | |
122 | * DDR Setup | |
123 | */ | |
124 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ | |
125 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
126 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
127 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
128 | #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ | |
129 | | DDRCDR_PZ_LOZ \ | |
130 | | DDRCDR_NZ_LOZ \ | |
131 | | DDRCDR_ODT \ | |
132 | | DDRCDR_Q_DRN) | |
133 | /* 0x7b880001 */ | |
134 | /* | |
135 | * Manually set up DDR parameters | |
136 | * consist of one chip NT5TU64M16HG from NANYA | |
137 | */ | |
138 | ||
139 | #define CONFIG_SYS_DDR_SIZE 128 /* MB */ | |
140 | ||
141 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 | |
142 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
143 | | CSCONFIG_ODT_RD_NEVER \ | |
144 | | CSCONFIG_ODT_WR_ONLY_CURRENT \ | |
145 | | CSCONFIG_BANK_BIT_3 \ | |
146 | | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) | |
147 | /* 0x80010102 */ | |
148 | #define CONFIG_SYS_DDR_TIMING_3 0 | |
149 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | |
150 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
151 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
152 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
153 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
154 | | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
155 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
156 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
157 | /* 0x00260802 */ | |
158 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ | |
159 | | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
160 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
161 | | (7 << TIMING_CFG1_CASLAT_SHIFT) \ | |
162 | | (9 << TIMING_CFG1_REFREC_SHIFT) \ | |
163 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
164 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
165 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
166 | /* 0x26279222 */ | |
167 | #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ | |
168 | | (4 << TIMING_CFG2_CPO_SHIFT) \ | |
169 | | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
170 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
171 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
172 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
173 | | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
174 | /* 0x021848c5 */ | |
175 | #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ | |
176 | | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
177 | /* 0x08240100 */ | |
178 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | |
179 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ | |
180 | | SDRAM_CFG_DBW_16) | |
181 | /* 0x43100000 */ | |
182 | ||
183 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ | |
184 | #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ | |
185 | | (0x0242 << SDRAM_MODE_SD_SHIFT)) | |
186 | /* ODT 150ohm CL=4, AL=0 on SDRAM */ | |
187 | #define CONFIG_SYS_DDR_MODE2 0x00000000 | |
188 | ||
189 | /* | |
190 | * Memory test | |
191 | */ | |
192 | #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ | |
193 | #define CONFIG_SYS_MEMTEST_END 0x07f00000 | |
194 | ||
195 | /* | |
196 | * The reserved memory | |
197 | */ | |
198 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
199 | ||
200 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ | |
201 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
202 | ||
203 | /* | |
204 | * Initial RAM Base Address Setup | |
205 | */ | |
206 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
207 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
208 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ | |
209 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
210 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
211 | ||
212 | /* | |
213 | * Local Bus Configuration & Clock Setup | |
214 | */ | |
215 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP | |
216 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
217 | #define CONFIG_SYS_LBC_LBCR 0x00040000 | |
218 | ||
219 | /* | |
220 | * FLASH on the Local Bus | |
221 | */ | |
a3f9d6c7 DE |
222 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
223 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
224 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
225 | #define CONFIG_FLASH_CFI_LEGACY | |
226 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
a3f9d6c7 DE |
227 | |
228 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
229 | #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ | |
230 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
231 | ||
232 | /* Window base at flash base */ | |
233 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
234 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) | |
235 | ||
236 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ | |
237 | | BR_PS_16 /* 16 bit port */ \ | |
238 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
239 | | BR_V) /* valid */ | |
240 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
241 | | OR_UPM_XAM \ | |
242 | | OR_GPCM_CSNT \ | |
243 | | OR_GPCM_ACS_DIV2 \ | |
244 | | OR_GPCM_XACS \ | |
245 | | OR_GPCM_SCY_15 \ | |
246 | | OR_GPCM_TRLX_SET \ | |
247 | | OR_GPCM_EHTR_SET) | |
248 | ||
249 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
250 | #define CONFIG_SYS_MAX_FLASH_SECT 135 | |
251 | ||
252 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
253 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
254 | ||
255 | /* | |
256 | * FPGA | |
257 | */ | |
258 | #define CONFIG_SYS_FPGA0_BASE 0xE0600000 | |
259 | #define CONFIG_SYS_FPGA0_SIZE 1 /* FPGA size is 1M */ | |
260 | ||
261 | /* Window base at FPGA base */ | |
262 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA0_BASE | |
263 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_1MB) | |
264 | ||
265 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA0_BASE \ | |
266 | | BR_PS_16 /* 16 bit port */ \ | |
267 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
268 | | BR_V) /* valid */ | |
a119357c RP |
269 | |
270 | #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_FPGA0_SIZE) \ | |
a3f9d6c7 DE |
271 | | OR_UPM_XAM \ |
272 | | OR_GPCM_CSNT \ | |
a119357c RP |
273 | | OR_GPCM_SCY_5 \ |
274 | | OR_GPCM_TRLX_CLEAR \ | |
275 | | OR_GPCM_EHTR_CLEAR) | |
a3f9d6c7 DE |
276 | |
277 | #define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE | |
278 | #define CONFIG_SYS_FPGA_DONE(k) 0x0010 | |
279 | ||
280 | #define CONFIG_SYS_FPGA_COUNT 1 | |
281 | ||
282 | #define CONFIG_SYS_MCLINK_MAX 3 | |
283 | ||
284 | #define CONFIG_SYS_FPGA_PTR \ | |
285 | { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } | |
286 | ||
287 | #define CONFIG_SYS_FPGA_NO_RFL_HI | |
288 | ||
289 | /* | |
290 | * Serial Port | |
291 | */ | |
292 | #define CONFIG_CONS_INDEX 2 | |
a3f9d6c7 DE |
293 | #define CONFIG_SYS_NS16550_SERIAL |
294 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
295 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
296 | ||
297 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
298 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
299 | ||
300 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) | |
301 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
302 | ||
a3f9d6c7 | 303 | /* Pass open firmware flat tree */ |
a3f9d6c7 DE |
304 | |
305 | /* I2C */ | |
306 | #define CONFIG_SYS_I2C | |
307 | #define CONFIG_SYS_I2C_FSL | |
308 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
309 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
310 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
311 | ||
312 | #define CONFIG_PCA953X /* NXP PCA9554 */ | |
47098056 DE |
313 | #define CONFIG_CMD_PCA953X |
314 | #define CONFIG_CMD_PCA953X_INFO | |
315 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ | |
316 | {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } | |
317 | ||
a3f9d6c7 DE |
318 | #define CONFIG_PCA9698 /* NXP PCA9698 */ |
319 | ||
320 | #define CONFIG_SYS_I2C_IHS | |
321 | #define CONFIG_SYS_I2C_IHS_CH0 | |
322 | #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 | |
323 | #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F | |
324 | #define CONFIG_SYS_I2C_IHS_CH1 | |
325 | #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 | |
326 | #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F | |
327 | #define CONFIG_SYS_I2C_IHS_CH2 | |
328 | #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 | |
329 | #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F | |
330 | #define CONFIG_SYS_I2C_IHS_CH3 | |
331 | #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 | |
332 | #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F | |
333 | ||
1d2541ba DE |
334 | #ifdef CONFIG_STRIDER_CON_DP |
335 | #define CONFIG_SYS_I2C_IHS_DUAL | |
336 | #define CONFIG_SYS_I2C_IHS_CH0_1 | |
337 | #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 | |
338 | #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F | |
339 | #define CONFIG_SYS_I2C_IHS_CH1_1 | |
340 | #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 | |
341 | #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F | |
342 | #define CONFIG_SYS_I2C_IHS_CH2_1 | |
343 | #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 | |
344 | #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F | |
345 | #define CONFIG_SYS_I2C_IHS_CH3_1 | |
346 | #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 | |
347 | #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F | |
348 | #endif | |
349 | ||
a3f9d6c7 DE |
350 | /* |
351 | * Software (bit-bang) I2C driver configuration | |
352 | */ | |
353 | #define CONFIG_SYS_I2C_SOFT | |
354 | #define CONFIG_SOFT_I2C_READ_REPEATED_START | |
355 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
356 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F | |
357 | #define I2C_SOFT_DECLARATIONS2 | |
358 | #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 | |
359 | #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F | |
360 | #define I2C_SOFT_DECLARATIONS3 | |
361 | #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 | |
362 | #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F | |
363 | #define I2C_SOFT_DECLARATIONS4 | |
364 | #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 | |
365 | #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F | |
1d2541ba | 366 | #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) |
a3f9d6c7 DE |
367 | #define I2C_SOFT_DECLARATIONS5 |
368 | #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 | |
369 | #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F | |
370 | #define I2C_SOFT_DECLARATIONS6 | |
371 | #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 | |
372 | #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F | |
373 | #define I2C_SOFT_DECLARATIONS7 | |
374 | #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 | |
375 | #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F | |
376 | #define I2C_SOFT_DECLARATIONS8 | |
377 | #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 | |
378 | #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F | |
379 | #endif | |
1d2541ba DE |
380 | #ifdef CONFIG_STRIDER_CON_DP |
381 | #define I2C_SOFT_DECLARATIONS9 | |
382 | #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 | |
383 | #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F | |
384 | #define I2C_SOFT_DECLARATIONS10 | |
385 | #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 | |
386 | #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F | |
387 | #define I2C_SOFT_DECLARATIONS11 | |
388 | #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 | |
389 | #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F | |
390 | #define I2C_SOFT_DECLARATIONS12 | |
391 | #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 | |
392 | #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F | |
393 | #endif | |
a3f9d6c7 DE |
394 | |
395 | #ifdef CONFIG_STRIDER_CON | |
396 | #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} | |
397 | #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} | |
398 | #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} | |
399 | #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} | |
1d2541ba DE |
400 | #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ |
401 | {12, 0x4c} } | |
402 | #elif defined(CONFIG_STRIDER_CON_DP) | |
403 | #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} | |
404 | #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} | |
405 | #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} | |
406 | #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} | |
a3f9d6c7 DE |
407 | #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ |
408 | {12, 0x4c} } | |
145510cc DE |
409 | #elif defined(CONFIG_STRIDER_CPU_DP) |
410 | #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} | |
411 | #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} | |
412 | #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} | |
413 | #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ | |
414 | {8, 0x4c} } | |
a3f9d6c7 DE |
415 | #else |
416 | #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} | |
417 | #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} | |
418 | #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} | |
419 | #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ | |
420 | {4, 0x18} } | |
421 | #endif | |
422 | ||
423 | #ifndef __ASSEMBLY__ | |
424 | void fpga_gpio_set(unsigned int bus, int pin); | |
425 | void fpga_gpio_clear(unsigned int bus, int pin); | |
426 | int fpga_gpio_get(unsigned int bus, int pin); | |
1d2541ba DE |
427 | void fpga_control_set(unsigned int bus, int pin); |
428 | void fpga_control_clear(unsigned int bus, int pin); | |
a3f9d6c7 DE |
429 | #endif |
430 | ||
431 | #ifdef CONFIG_STRIDER_CON | |
432 | #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) | |
433 | #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) | |
434 | #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ | |
435 | (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) | |
1d2541ba DE |
436 | #elif defined(CONFIG_STRIDER_CON_DP) |
437 | #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) | |
438 | #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) | |
439 | #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) | |
a3f9d6c7 DE |
440 | #else |
441 | #define I2C_SDA_GPIO 0x0040 | |
442 | #define I2C_SCL_GPIO 0x0020 | |
443 | #define I2C_FPGA_IDX I2C_ADAP_HWNR | |
444 | #endif | |
1d2541ba DE |
445 | |
446 | #ifdef CONFIG_STRIDER_CON_DP | |
447 | #define I2C_ACTIVE \ | |
448 | do { \ | |
449 | if (I2C_ADAP_HWNR > 7) \ | |
450 | fpga_control_set(I2C_FPGA_IDX, 0x0004); \ | |
451 | else \ | |
452 | fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ | |
453 | } while (0) | |
454 | #else | |
a3f9d6c7 | 455 | #define I2C_ACTIVE { } |
1d2541ba DE |
456 | #endif |
457 | ||
a3f9d6c7 DE |
458 | #define I2C_TRISTATE { } |
459 | #define I2C_READ \ | |
460 | (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) | |
461 | #define I2C_SDA(bit) \ | |
462 | do { \ | |
463 | if (bit) \ | |
464 | fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ | |
465 | else \ | |
466 | fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ | |
467 | } while (0) | |
468 | #define I2C_SCL(bit) \ | |
469 | do { \ | |
470 | if (bit) \ | |
471 | fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ | |
472 | else \ | |
473 | fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ | |
474 | } while (0) | |
475 | #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ | |
476 | ||
477 | /* | |
478 | * Software (bit-bang) MII driver configuration | |
479 | */ | |
480 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
481 | #define CONFIG_BITBANGMII_MULTI | |
482 | ||
483 | /* | |
484 | * OSD Setup | |
485 | */ | |
486 | #define CONFIG_SYS_OSD_SCREENS 1 | |
487 | #define CONFIG_SYS_DP501_DIFFERENTIAL | |
488 | #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ | |
489 | ||
1d2541ba DE |
490 | #ifdef CONFIG_STRIDER_CON_DP |
491 | #define CONFIG_SYS_OSD_DH | |
492 | #endif | |
493 | ||
a3f9d6c7 DE |
494 | /* |
495 | * General PCI | |
496 | * Addresses are mapped 1-1. | |
497 | */ | |
498 | #define CONFIG_SYS_PCIE1_BASE 0xA0000000 | |
499 | #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 | |
500 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 | |
501 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 | |
502 | #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 | |
503 | #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 | |
504 | #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 | |
505 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 | |
506 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 | |
507 | ||
508 | /* enable PCIE clock */ | |
509 | #define CONFIG_SYS_SCCR_PCIEXP1CM 1 | |
510 | ||
a3f9d6c7 DE |
511 | #define CONFIG_PCI_INDIRECT_BRIDGE |
512 | #define CONFIG_PCIE | |
513 | ||
514 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
515 | ||
516 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
517 | #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 | |
518 | ||
519 | /* | |
520 | * TSEC | |
521 | */ | |
522 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
523 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 | |
524 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
525 | ||
526 | /* | |
527 | * TSEC ethernet configuration | |
528 | */ | |
529 | #define CONFIG_MII 1 /* MII PHY management */ | |
530 | #define CONFIG_TSEC1 | |
531 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
532 | #define TSEC1_PHY_ADDR 1 | |
533 | #define TSEC1_PHYIDX 0 | |
534 | #define TSEC1_FLAGS 0 | |
535 | ||
536 | /* Options are: eTSEC[0-1] */ | |
537 | #define CONFIG_ETHPRIME "eTSEC0" | |
538 | ||
539 | /* | |
540 | * Environment | |
541 | */ | |
542 | #if 1 | |
543 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
544 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
545 | CONFIG_SYS_MONITOR_LEN) | |
546 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ | |
547 | #define CONFIG_ENV_SIZE 0x2000 | |
548 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) | |
549 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
550 | #else | |
551 | #define CONFIG_ENV_IS_NOWHERE | |
552 | #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ | |
553 | #endif | |
554 | ||
555 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
556 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
557 | ||
558 | /* | |
559 | * Command line configuration. | |
560 | */ | |
a3f9d6c7 | 561 | #define CONFIG_CMD_PCI |
a3f9d6c7 DE |
562 | |
563 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
564 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
565 | ||
566 | /* | |
567 | * Miscellaneous configurable options | |
568 | */ | |
569 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
570 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
571 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
572 | ||
a3f9d6c7 DE |
573 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
574 | ||
a3f9d6c7 DE |
575 | /* Print Buffer Size */ |
576 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
577 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
578 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
579 | ||
580 | /* | |
581 | * For booting Linux, the board info and command line data | |
582 | * have to be in the first 256 MB of memory, since this is | |
583 | * the maximum mapped by the Linux kernel during initialization. | |
584 | */ | |
585 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ | |
586 | ||
587 | /* | |
588 | * Core HID Setup | |
589 | */ | |
590 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
591 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
592 | HID0_ENABLE_INSTRUCTION_CACHE | \ | |
593 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) | |
594 | #define CONFIG_SYS_HID2 HID2_HBE | |
595 | ||
596 | /* | |
597 | * MMU Setup | |
598 | */ | |
599 | ||
600 | /* DDR: cache cacheable */ | |
601 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ | |
602 | BATL_MEMCOHERENCE) | |
603 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ | |
604 | BATU_VS | BATU_VP) | |
605 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
606 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
607 | ||
608 | /* IMMRBAR, PCI IO and FPGA: cache-inhibit and guarded */ | |
609 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ | |
610 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
611 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ | |
612 | BATU_VP) | |
613 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
614 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
615 | ||
616 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
617 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ | |
618 | BATL_MEMCOHERENCE) | |
619 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ | |
620 | BATU_VS | BATU_VP) | |
621 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ | |
622 | BATL_CACHEINHIBIT | \ | |
623 | BATL_GUARDEDSTORAGE) | |
624 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
625 | ||
626 | /* Stack in dcache: cacheable, no memory coherence */ | |
627 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) | |
628 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ | |
629 | BATU_VS | BATU_VP) | |
630 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
631 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
632 | ||
633 | /* | |
634 | * Environment Configuration | |
635 | */ | |
636 | ||
637 | #define CONFIG_ENV_OVERWRITE | |
638 | ||
639 | #if defined(CONFIG_TSEC_ENET) | |
640 | #define CONFIG_HAS_ETH0 | |
641 | #endif | |
642 | ||
643 | #define CONFIG_BAUDRATE 115200 | |
644 | ||
645 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ | |
646 | ||
a3f9d6c7 DE |
647 | |
648 | #define CONFIG_HOSTNAME hrcon | |
649 | #define CONFIG_ROOTPATH "/opt/nfsroot" | |
650 | #define CONFIG_BOOTFILE "uImage" | |
651 | ||
652 | #define CONFIG_PREBOOT /* enable preboot variable */ | |
653 | ||
654 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
655 | "netdev=eth0\0" \ | |
656 | "consoledev=ttyS1\0" \ | |
657 | "u-boot=u-boot.bin\0" \ | |
658 | "kernel_addr=1000000\0" \ | |
659 | "fdt_addr=C00000\0" \ | |
660 | "fdtfile=hrcon.dtb\0" \ | |
661 | "load=tftp ${loadaddr} ${u-boot}\0" \ | |
662 | "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ | |
663 | " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ | |
664 | " +${filesize};cp.b ${fileaddr} " \ | |
665 | __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ | |
666 | "upd=run load update\0" \ | |
667 | ||
668 | #define CONFIG_NFSBOOTCOMMAND \ | |
669 | "setenv bootargs root=/dev/nfs rw " \ | |
670 | "nfsroot=$serverip:$rootpath " \ | |
671 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
672 | "console=$consoledev,$baudrate $othbootargs;" \ | |
673 | "tftp ${kernel_addr} $bootfile;" \ | |
674 | "tftp ${fdt_addr} $fdtfile;" \ | |
675 | "bootm ${kernel_addr} - ${fdt_addr}" | |
676 | ||
677 | #define CONFIG_MMCBOOTCOMMAND \ | |
678 | "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ | |
679 | "console=$consoledev,$baudrate $othbootargs;" \ | |
680 | "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ | |
681 | "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ | |
682 | "bootm ${kernel_addr} - ${fdt_addr}" | |
683 | ||
684 | #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND | |
685 | ||
a3f9d6c7 | 686 | #endif /* __CONFIG_H */ |