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cba69eee IC |
1 | /* |
2 | * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> | |
3 | * | |
4 | * (C) Copyright 2007-2011 | |
5 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
6 | * Tom Cubie <tangliang@allwinnertech.com> | |
7 | * | |
8 | * Configuration settings for the Allwinner sunxi series of boards. | |
9 | * | |
10 | * SPDX-License-Identifier: GPL-2.0+ | |
11 | */ | |
12 | ||
13 | #ifndef _SUNXI_COMMON_CONFIG_H | |
14 | #define _SUNXI_COMMON_CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
19 | #define CONFIG_SUNXI /* sunxi family */ | |
50827a59 IC |
20 | #ifdef CONFIG_SPL_BUILD |
21 | #ifndef CONFIG_SPL_FEL | |
22 | #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ | |
23 | #endif | |
24 | #endif | |
cba69eee IC |
25 | |
26 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
27 | ||
28 | #define CONFIG_SYS_TEXT_BASE 0x4a000000 | |
29 | ||
30 | /* | |
31 | * Display CPU information | |
32 | */ | |
33 | #define CONFIG_DISPLAY_CPUINFO | |
34 | ||
35 | /* Serial & console */ | |
36 | #define CONFIG_SYS_NS16550 | |
37 | #define CONFIG_SYS_NS16550_SERIAL | |
38 | /* ns16550 reg in the low bits of cpu reg */ | |
39 | #define CONFIG_SYS_NS16550_REG_SIZE -4 | |
40 | #define CONFIG_SYS_NS16550_CLK 24000000 | |
41 | #define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE | |
42 | #define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE | |
43 | #define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE | |
44 | #define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE | |
45 | ||
46 | /* DRAM Base */ | |
47 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
48 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0 | |
49 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ | |
50 | ||
51 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
52 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
53 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
54 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
55 | ||
56 | #define CONFIG_NR_DRAM_BANKS 1 | |
57 | #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE | |
58 | #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ | |
59 | ||
60 | #define CONFIG_CMD_MEMORY | |
61 | #define CONFIG_CMD_SETEXPR | |
62 | ||
63 | #define CONFIG_SETUP_MEMORY_TAGS | |
64 | #define CONFIG_CMDLINE_TAG | |
65 | #define CONFIG_INITRD_TAG | |
66 | ||
e24ea55c IC |
67 | /* mmc config */ |
68 | #define CONFIG_MMC | |
69 | #define CONFIG_GENERIC_MMC | |
70 | #define CONFIG_CMD_MMC | |
71 | #define CONFIG_MMC_SUNXI | |
72 | #define CONFIG_MMC_SUNXI_SLOT 0 | |
e24ea55c IC |
73 | #define CONFIG_ENV_IS_IN_MMC |
74 | #define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ | |
75 | ||
cba69eee IC |
76 | /* 4MB of malloc() pool */ |
77 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) | |
78 | ||
79 | /* | |
80 | * Miscellaneous configurable options | |
81 | */ | |
82 | #define CONFIG_CMD_ECHO | |
83 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
84 | #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ | |
85 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
86 | #define CONFIG_SYS_GENERIC_BOARD | |
87 | ||
88 | /* Boot Argument Buffer Size */ | |
89 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
90 | ||
91 | #define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */ | |
92 | ||
93 | /* standalone support */ | |
94 | #define CONFIG_STANDALONE_LOAD_ADDR 0x48000000 | |
95 | ||
96 | #define CONFIG_SYS_HZ 1000 | |
97 | ||
98 | /* baudrate */ | |
99 | #define CONFIG_BAUDRATE 115200 | |
100 | ||
101 | /* The stack sizes are set up in start.S using the settings below */ | |
102 | #define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ | |
103 | ||
104 | /* FLASH and environment organization */ | |
105 | ||
106 | #define CONFIG_SYS_NO_FLASH | |
107 | ||
108 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ | |
109 | #define CONFIG_IDENT_STRING " Allwinner Technology" | |
110 | ||
e24ea55c | 111 | #define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ |
cba69eee IC |
112 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ |
113 | ||
114 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
115 | "bootm_size=0x10000000\0" | |
116 | ||
117 | #define CONFIG_SYS_BOOT_GET_CMDLINE | |
118 | ||
119 | #include <config_cmd_default.h> | |
120 | ||
121 | #define CONFIG_FAT_WRITE /* enable write access */ | |
122 | ||
123 | #define CONFIG_SPL_FRAMEWORK | |
124 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
125 | #define CONFIG_SPL_SERIAL_SUPPORT | |
126 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
127 | ||
50827a59 IC |
128 | #ifdef CONFIG_SPL_FEL |
129 | ||
cba69eee IC |
130 | #define CONFIG_SPL |
131 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" | |
132 | #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" | |
133 | #define CONFIG_SPL_TEXT_BASE 0x2000 | |
134 | #define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ | |
50827a59 IC |
135 | |
136 | #else /* CONFIG_SPL */ | |
137 | ||
138 | #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 | |
139 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ | |
140 | ||
141 | #define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ | |
142 | #define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ | |
143 | ||
144 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
145 | #define CONFIG_SPL_MMC_SUPPORT | |
146 | ||
147 | #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" | |
148 | ||
149 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ | |
150 | #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ | |
151 | ||
152 | #endif /* CONFIG_SPL */ | |
153 | ||
cba69eee IC |
154 | /* end of 32 KiB in sram */ |
155 | #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ | |
156 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK | |
157 | #define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000 | |
158 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */ | |
159 | ||
160 | #undef CONFIG_CMD_FPGA | |
161 | #undef CONFIG_CMD_NET | |
162 | #undef CONFIG_CMD_NFS | |
163 | ||
6620377e HG |
164 | /* I2C */ |
165 | #define CONFIG_SPL_I2C_SUPPORT | |
166 | #define CONFIG_SYS_I2C | |
167 | #define CONFIG_SYS_I2C_MVTWSI | |
168 | #define CONFIG_SYS_I2C_SPEED 400000 | |
169 | #define CONFIG_SYS_I2C_SLAVE 0x7f | |
170 | #define CONFIG_CMD_I2C | |
171 | ||
14bc66bd HN |
172 | /* PMU */ |
173 | #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER | |
174 | #define CONFIG_SPL_POWER_SUPPORT | |
175 | #endif | |
176 | ||
f84269c5 | 177 | #ifndef CONFIG_CONS_INDEX |
cba69eee | 178 | #define CONFIG_CONS_INDEX 1 /* UART0 */ |
f84269c5 | 179 | #endif |
cba69eee | 180 | |
c26fb9db HG |
181 | /* Ethernet support */ |
182 | #ifdef CONFIG_SUNXI_EMAC | |
183 | #define CONFIG_MII /* MII PHY management */ | |
184 | #endif | |
185 | ||
5835823d IC |
186 | #ifdef CONFIG_SUNXI_GMAC |
187 | #define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */ | |
188 | #define CONFIG_DW_AUTONEG | |
189 | #define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */ | |
190 | #define CONFIG_PHY_ADDR 1 | |
191 | #define CONFIG_MII /* MII PHY management */ | |
192 | #define CONFIG_PHYLIB | |
193 | #endif | |
194 | ||
195 | #ifdef CONFIG_CMD_NET | |
196 | #define CONFIG_CMD_NFS | |
197 | #define CONFIG_CMD_DNS | |
198 | #define CONFIG_NETCONSOLE | |
199 | #define CONFIG_BOOTP_DNS2 | |
200 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
201 | #endif | |
202 | ||
cba69eee IC |
203 | #if !defined CONFIG_ENV_IS_IN_MMC && \ |
204 | !defined CONFIG_ENV_IS_IN_NAND && \ | |
205 | !defined CONFIG_ENV_IS_IN_FAT && \ | |
206 | !defined CONFIG_ENV_IS_IN_SPI_FLASH | |
207 | #define CONFIG_ENV_IS_NOWHERE | |
208 | #endif | |
209 | ||
b41d7d05 JL |
210 | #define CONFIG_MISC_INIT_R |
211 | ||
cba69eee IC |
212 | #ifndef CONFIG_SPL_BUILD |
213 | #include <config_distro_defaults.h> | |
214 | #endif | |
215 | ||
216 | #endif /* _SUNXI_COMMON_CONFIG_H */ |