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dc7c9a1a WD |
1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
dc7c9a1a WD |
6 | */ |
7 | ||
8 | /* | |
9 | * board/config.h - configuration options, board specific, | |
10 | * for SinoVee Microsystems SC8xx series SBC | |
11 | * http://www.fel.com.cn (Chinese) | |
12 | * http://www.sinovee.com (English) | |
13 | */ | |
14 | ||
15 | #ifndef __CONFIG_H | |
16 | #define __CONFIG_H | |
17 | ||
2ae18241 WD |
18 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
19 | ||
dc7c9a1a WD |
20 | /* Custom configuration */ |
21 | /* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ | |
22 | /* SC85T,SC860T, FEL8xx-AT(855T/860T) */ | |
23 | /*#define CONFIG_FEL8xx_AT */ | |
24 | /*#define CONFIG_LCD */ | |
59155f4c | 25 | /*#define CONFIG_MPC8XX_LCD*/ |
dc7c9a1a WD |
26 | /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ |
27 | /* #define CONFIG_50MHz */ | |
28 | /* #define CONFIG_66MHz */ | |
29 | /* #define CONFIG_75MHz */ | |
30 | #define CONFIG_80MHz | |
31 | /*#define CONFIG_100MHz */ | |
32 | /* #define CONFIG_BUS_DIV2 1 */ | |
33 | /* for BOOT device port size */ | |
34 | /* #define CONFIG_BOOT_8B */ | |
35 | #define CONFIG_BOOT_16B | |
36 | /* #define CONFIG_BOOT_32B */ | |
37 | /* #define CONFIG_CAN_DRIVER */ | |
38 | /* #define DEBUG */ | |
39 | #define CONFIG_FEC_ENET | |
40 | ||
41 | /* #define CONFIG_SDRAM_16M */ | |
42 | #define CONFIG_SDRAM_32M | |
43 | /* #define CONFIG_SDRAM_64M */ | |
6d0f6bcf | 44 | #define CONFIG_SYS_RESET_ADDRESS 0xffffffff |
dc7c9a1a WD |
45 | /* |
46 | * High Level Configuration Options | |
47 | * (easy to change) | |
48 | */ | |
49 | ||
50 | /* #define CONFIG_MPC823 1 */ | |
51 | /* #define CONFIG_MPC850 1 */ | |
52 | #define CONFIG_MPC855 1 | |
53 | /* #define CONFIG_MPC860 1 */ | |
54 | /* #define CONFIG_MPC860T 1 */ | |
55 | ||
56 | #undef CONFIG_WATCHDOG /* watchdog */ | |
57 | ||
53677ef1 | 58 | #define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ |
dc7c9a1a WD |
59 | |
60 | #ifdef CONFIG_LCD /* with LCD controller ? */ | |
fd3103bb | 61 | /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ |
dc7c9a1a WD |
62 | #endif |
63 | ||
64 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
65 | #undef CONFIG_8xx_CONS_SMC2 | |
66 | #undef CONFIG_8xx_CONS_NONE | |
67 | #define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ | |
68 | #if 0 | |
69 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
70 | #else | |
71 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
72 | #endif | |
73 | ||
74 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
75 | ||
76 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
77 | ||
78 | #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" | |
79 | ||
80 | #undef CONFIG_BOOTARGS | |
81 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8bde7f77 | 82 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 83 | "nfsroot=${serverip}:${rootpath}\0" \ |
8bde7f77 | 84 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
85 | "addip=setenv bootargs ${bootargs} " \ |
86 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
87 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8bde7f77 | 88 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 89 | "bootm ${kernel_addr}\0" \ |
8bde7f77 | 90 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
91 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
92 | "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ | |
8bde7f77 WD |
93 | "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ |
94 | "bootfile=pImage-sc855t\0" \ | |
95 | "kernel_addr=48000000\0" \ | |
96 | "ramdisk_addr=48100000\0" \ | |
97 | "" | |
dc7c9a1a | 98 | #define CONFIG_BOOTCOMMAND \ |
53677ef1 WD |
99 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
100 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
dc7c9a1a WD |
101 | "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" |
102 | ||
103 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 104 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
dc7c9a1a WD |
105 | |
106 | ||
107 | #ifdef CONFIG_LCD | |
108 | # undef CONFIG_STATUS_LED /* disturbs display */ | |
109 | #else | |
110 | # define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
111 | #endif /* CONFIG_LCD */ | |
112 | ||
113 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
114 | ||
d3b8c1a7 JL |
115 | /* |
116 | * BOOTP options | |
117 | */ | |
118 | #define CONFIG_BOOTP_SUBNETMASK | |
119 | #define CONFIG_BOOTP_GATEWAY | |
120 | #define CONFIG_BOOTP_HOSTNAME | |
121 | #define CONFIG_BOOTP_BOOTPATH | |
122 | #define CONFIG_BOOTP_BOOTFILESIZE | |
dc7c9a1a WD |
123 | |
124 | #define CONFIG_MAC_PARTITION | |
125 | #define CONFIG_DOS_PARTITION | |
126 | ||
127 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
128 | ||
46da1e96 JL |
129 | |
130 | /* | |
131 | * Command line configuration. | |
132 | */ | |
133 | #include <config_cmd_default.h> | |
134 | ||
135 | #define CONFIG_CMD_ASKENV | |
136 | #define CONFIG_CMD_DHCP | |
46da1e96 JL |
137 | #define CONFIG_CMD_DATE |
138 | ||
dc7c9a1a WD |
139 | /* |
140 | * Miscellaneous configurable options | |
141 | */ | |
6d0f6bcf | 142 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
dc7c9a1a | 143 | |
6d0f6bcf | 144 | #ifdef CONFIG_SYS_HUSH_PARSER |
dc7c9a1a WD |
145 | #endif |
146 | ||
46da1e96 | 147 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 148 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
dc7c9a1a | 149 | #else |
6d0f6bcf | 150 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
dc7c9a1a | 151 | #endif |
6d0f6bcf JCPV |
152 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
153 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
154 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
dc7c9a1a | 155 | |
6d0f6bcf JCPV |
156 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
157 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
dc7c9a1a | 158 | |
6d0f6bcf | 159 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
dc7c9a1a | 160 | |
dc7c9a1a WD |
161 | /* |
162 | * Low Level Configuration Settings | |
163 | * (address mappings, register initial values, etc.) | |
164 | * You should know what you are doing if you make changes here. | |
165 | */ | |
166 | /*----------------------------------------------------------------------- | |
167 | * Internal Memory Mapped Register | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_IMMR 0xFF000000 |
dc7c9a1a WD |
170 | |
171 | /*----------------------------------------------------------------------- | |
172 | * Definitions for initial stack pointer and data area (in DPRAM) | |
173 | */ | |
6d0f6bcf | 174 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 175 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 176 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 177 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
dc7c9a1a WD |
178 | |
179 | /*----------------------------------------------------------------------- | |
180 | * Start addresses for the final memory configuration | |
181 | * (Set up by the startup code) | |
6d0f6bcf | 182 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
dc7c9a1a | 183 | */ |
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
185 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
186 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ | |
187 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
188 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
dc7c9a1a WD |
189 | |
190 | /* | |
191 | * For booting Linux, the board info and command line data | |
192 | * have to be in the first 8 MB of memory, since this is | |
193 | * the maximum mapped by the Linux kernel during initialization. | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
dc7c9a1a WD |
196 | |
197 | /*----------------------------------------------------------------------- | |
198 | * FLASH organization | |
199 | */ | |
6d0f6bcf JCPV |
200 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
201 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
dc7c9a1a | 202 | |
6d0f6bcf JCPV |
203 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
204 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
dc7c9a1a | 205 | |
5a1aceb0 | 206 | #define CONFIG_ENV_IS_IN_FLASH 1 |
dc7c9a1a WD |
207 | |
208 | #ifdef CONFIG_BOOT_8B | |
0e8d1586 JCPV |
209 | #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
210 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
dc7c9a1a | 211 | #elif defined (CONFIG_BOOT_16B) |
0e8d1586 JCPV |
212 | #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
213 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
dc7c9a1a | 214 | #elif defined (CONFIG_BOOT_32B) |
0e8d1586 JCPV |
215 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
216 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
dc7c9a1a WD |
217 | #endif |
218 | ||
219 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
220 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
221 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
dc7c9a1a WD |
222 | |
223 | ||
224 | /*----------------------------------------------------------------------- | |
225 | * Hardware Information Block | |
226 | */ | |
6d0f6bcf JCPV |
227 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
228 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
229 | #define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ | |
dc7c9a1a WD |
230 | |
231 | /*----------------------------------------------------------------------- | |
232 | * Cache Configuration | |
233 | */ | |
6d0f6bcf | 234 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
46da1e96 | 235 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 236 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
dc7c9a1a WD |
237 | #endif |
238 | ||
239 | /*----------------------------------------------------------------------- | |
240 | * SYPCR - System Protection Control 11-9 | |
241 | * SYPCR can only be written once after reset! | |
242 | *----------------------------------------------------------------------- | |
243 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
244 | */ | |
245 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 246 | /*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
dc7c9a1a WD |
247 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
248 | */ | |
6d0f6bcf | 249 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ |
dc7c9a1a WD |
250 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
251 | #else | |
6d0f6bcf | 252 | #define CONFIG_SYS_SYPCR 0xffffff88 |
dc7c9a1a WD |
253 | #endif |
254 | ||
255 | /*----------------------------------------------------------------------- | |
256 | * SIUMCR - SIU Module Configuration 11-6 | |
257 | *----------------------------------------------------------------------- | |
258 | * PCMCIA config., multi-function pin tri-state | |
259 | */ | |
260 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
261 | /*#define CONFIG_SYS_SIUMCR 0x00610c00 */ |
262 | #define CONFIG_SYS_SIUMCR 0x00000000 | |
dc7c9a1a | 263 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 264 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
dc7c9a1a WD |
265 | #endif /* CONFIG_CAN_DRIVER */ |
266 | ||
267 | /*----------------------------------------------------------------------- | |
268 | * TBSCR - Time Base Status and Control 11-26 | |
269 | *----------------------------------------------------------------------- | |
270 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
271 | */ | |
6d0f6bcf | 272 | #define CONFIG_SYS_TBSCR 0x0001 |
dc7c9a1a WD |
273 | |
274 | /*----------------------------------------------------------------------- | |
275 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
276 | *----------------------------------------------------------------------- | |
277 | */ | |
6d0f6bcf | 278 | #define CONFIG_SYS_RTCSC 0x00c3 |
dc7c9a1a WD |
279 | |
280 | /*----------------------------------------------------------------------- | |
281 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
282 | *----------------------------------------------------------------------- | |
283 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
284 | */ | |
6d0f6bcf | 285 | #define CONFIG_SYS_PISCR 0x0000 |
dc7c9a1a WD |
286 | |
287 | /*----------------------------------------------------------------------- | |
288 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
289 | *----------------------------------------------------------------------- | |
290 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
291 | * interrupt status bit | |
292 | */ | |
293 | #if defined (CONFIG_100MHz) | |
6d0f6bcf | 294 | #define CONFIG_SYS_PLPRCR 0x06301000 |
dc7c9a1a WD |
295 | #define CONFIG_8xx_GCLK_FREQ 100000000 |
296 | #elif defined (CONFIG_80MHz) | |
6d0f6bcf | 297 | #define CONFIG_SYS_PLPRCR 0x04f01000 |
dc7c9a1a | 298 | #define CONFIG_8xx_GCLK_FREQ 80000000 |
8bde7f77 | 299 | #elif defined(CONFIG_75MHz) |
6d0f6bcf | 300 | #define CONFIG_SYS_PLPRCR 0x04a00100 |
dc7c9a1a | 301 | #define CONFIG_8xx_GCLK_FREQ 75000000 |
8bde7f77 | 302 | #elif defined(CONFIG_66MHz) |
6d0f6bcf | 303 | #define CONFIG_SYS_PLPRCR 0x04101000 |
dc7c9a1a | 304 | #define CONFIG_8xx_GCLK_FREQ 66000000 |
8bde7f77 | 305 | #elif defined(CONFIG_50MHz) |
6d0f6bcf | 306 | #define CONFIG_SYS_PLPRCR 0x03101000 |
dc7c9a1a | 307 | #define CONFIG_8xx_GCLK_FREQ 50000000 |
8bde7f77 | 308 | #endif |
dc7c9a1a WD |
309 | |
310 | /*----------------------------------------------------------------------- | |
311 | * SCCR - System Clock and reset Control Register 15-27 | |
312 | *----------------------------------------------------------------------- | |
313 | * Set clock output, timebase and RTC source and divider, | |
314 | * power management and some other internal clocks | |
315 | */ | |
316 | #define SCCR_MASK SCCR_EBDF11 | |
8bde7f77 | 317 | #ifdef CONFIG_BUS_DIV2 |
6d0f6bcf | 318 | #define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL |
dc7c9a1a | 319 | #else /* up to 50 MHz we use a 1:1 clock */ |
6d0f6bcf | 320 | #define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL |
8bde7f77 | 321 | #endif |
dc7c9a1a WD |
322 | |
323 | /*----------------------------------------------------------------------- | |
324 | * PCMCIA stuff | |
325 | *----------------------------------------------------------------------- | |
326 | * | |
327 | */ | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
329 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
330 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
331 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
332 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
333 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
334 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
335 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
dc7c9a1a WD |
336 | |
337 | /*----------------------------------------------------------------------- | |
338 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
339 | *----------------------------------------------------------------------- | |
340 | */ | |
341 | ||
53677ef1 | 342 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
dc7c9a1a | 343 | |
8d1165e1 PH |
344 | #define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ |
345 | #define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */ | |
dc7c9a1a WD |
346 | #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ |
347 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
348 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
349 | ||
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
351 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
dc7c9a1a | 352 | |
6d0f6bcf JCPV |
353 | #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010 |
354 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
355 | /*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */ | |
356 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O | |
dc7c9a1a | 357 | */ |
6d0f6bcf | 358 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses |
dc7c9a1a | 359 | */ |
6d0f6bcf | 360 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers |
dc7c9a1a | 361 | */ |
8bde7f77 | 362 | #define CONFIG_ATAPI |
6d0f6bcf | 363 | #define CONFIG_SYS_PIO_MODE 0 |
dc7c9a1a WD |
364 | |
365 | /*----------------------------------------------------------------------- | |
366 | * | |
367 | *----------------------------------------------------------------------- | |
368 | * | |
369 | */ | |
6d0f6bcf JCPV |
370 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
371 | #define CONFIG_SYS_DER 0x0 | |
dc7c9a1a WD |
372 | |
373 | /* | |
374 | * Init Memory Controller: | |
375 | * | |
376 | * BR0/1 and OR0/1 (FLASH) | |
377 | */ | |
378 | ||
379 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
380 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
381 | ||
382 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
383 | * restrict access enough to keep SRAM working (if any) | |
384 | * but not too much to meddle with FLASH accesses | |
385 | */ | |
6d0f6bcf JCPV |
386 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
387 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
dc7c9a1a WD |
388 | |
389 | /* | |
390 | * FLASH timing: | |
391 | */ | |
8bde7f77 | 392 | #if defined(CONFIG_100MHz) |
6d0f6bcf JCPV |
393 | #define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4 |
394 | #define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 | |
395 | #define CONFIG_SYS_MxMR_PTx 0x61000000 | |
396 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
397 | |
398 | #elif defined(CONFIG_80MHz) | |
6d0f6bcf JCPV |
399 | #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 |
400 | #define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 | |
401 | #define CONFIG_SYS_MxMR_PTx 0x4e000000 | |
402 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a | 403 | |
8bde7f77 | 404 | #elif defined(CONFIG_75MHz) |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4 |
406 | #define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 | |
407 | #define CONFIG_SYS_MxMR_PTx 0x49000000 | |
408 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
409 | |
410 | #elif defined(CONFIG_66MHz) | |
6d0f6bcf | 411 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
8bde7f77 | 412 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
6d0f6bcf JCPV |
413 | /*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */ |
414 | #define CONFIG_SYS_OR_TIMING_DOC 0x000003f4 | |
415 | #define CONFIG_SYS_MxMR_PTx 0x40000000 | |
416 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
417 | |
418 | #else /* 50 MHz */ | |
6d0f6bcf JCPV |
419 | #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 |
420 | #define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 | |
421 | #define CONFIG_SYS_MxMR_PTx 0x30000000 | |
422 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
423 | #endif /*CONFIG_??MHz */ |
424 | ||
425 | ||
426 | #if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ | |
6d0f6bcf JCPV |
427 | #define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH) |
428 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) | |
dc7c9a1a | 429 | #elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ |
6d0f6bcf JCPV |
430 | #define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH) |
431 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) | |
dc7c9a1a | 432 | #elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ |
6d0f6bcf JCPV |
433 | #define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH) |
434 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
dc7c9a1a WD |
435 | #else |
436 | #error Boot device port size missing. | |
437 | #endif | |
438 | ||
439 | /* | |
440 | * Disk-On-Chip configuration | |
441 | */ | |
442 | ||
6d0f6bcf JCPV |
443 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT |
444 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
dc7c9a1a | 445 | |
6d0f6bcf JCPV |
446 | #define CONFIG_SYS_DOC_SUPPORT_2000 |
447 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
448 | #define CONFIG_SYS_DOC_BASE 0x80000000 | |
dc7c9a1a | 449 | |
dc7c9a1a | 450 | #endif /* __CONFIG_H */ |