[people/ms/u-boot.git] / include / configs / tam3517-common.h

/*
 * Copyright (C) 2011
 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
 *
 * Copyright (C) 2009 TechNexion Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc.
 */

#ifndef __TAM3517_H
#define __TAM3517_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		/* in a TI OMAP core */
#define CONFIG_OMAP34XX		/* which is a 34XX */
#define CONFIG_OMAP_GPIO

#define CONFIG_SYS_TEXT_BASE 0x80008000

#define CONFIG_SYS_CACHELINE_SIZE	64

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
					2 * 1024 * 1024)
/*
 * DDR related
 */
#define CONFIG_OMAP3_MICRON_DDR		/* Micron DDR */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550_COM1		OMAP34XX_UART1
#define CONFIG_SERIAL1			/* UART1 */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DOS_PARTITION

/* EHCI */
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_STORAGE

/* #define CONFIG_EHCI_DCACHE */

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB

#undef CONFIG_CMD_FLASH		/* only NAND on the SOM */
#undef CONFIG_CMD_IMLS

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_SYS_I2C_BUS		0
#define CONFIG_SYS_I2C_BUS_SELECT	1
#define CONFIG_DRIVER_OMAP34XX_I2C


/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */

#define CONFIG_AUTO_COMPLETE

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M

#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT
#define CONFIG_ENV_IS_IN_NAND
#define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */

/* Redundant Environment */
#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
						2 * CONFIG_SYS_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/*
 * ethernet support, EMAC
 *
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_DRIVER_TI_EMAC_USE_RMII
#define CONFIG_MII
#define CONFIG_EMAC_MDIO_PHY_NUM	0
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT 10

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_CONSOLE
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SPL_NAND_WORKSPACE	0x8f07f000 /* below BSS */

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000

/* NAND boot config */
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
					 48, 49, 50, 51, 52, 53, 54, 55,\
					 56, 57, 58, 59, 60, 61, 62, 63}
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000

#define CONFIG_OF_LIBFDT
#define CONFIG_FIT
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define CONFIG_MTD_PARTITIONS
#define CONFIG_MTD_DEVICE
#define CONFIG_CMD_MTDPARTS

/* Setup MTD for NAND on the SOM */
#define MTDIDS_DEFAULT		"nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT	"mtdparts=omap2-nand.0:512k(MLO)," \
				"1m(u-boot),256k(env1)," \
				"256k(env2),6m(kernel),-(rootfs)"

#define xstr(s)	str(s)
#define str(s)	#s

#define	CONFIG_TAM3517_SETTINGS						\
	"netdev=eth0\0"							\
	"nandargs=setenv bootargs root=${nandroot} "			\
		"rootfstype=${nandrootfstype}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip_sta=setenv bootargs ${bootargs} "			\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0"		\
	"addip=if test -n ${ipdyn};then run addip_dyn;"			\
		"else run addip_sta;fi\0"				\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=ttyO0,${baudrate}\0"				\
	"addmisc=setenv bootargs ${bootargs} ${misc}\0"			\
	"loadaddr=82000000\0"						\
	"kernel_addr_r=82000000\0"					\
	"hostname=" xstr(CONFIG_HOSTNAME) "\0"				\
	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0"			\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr}\0"				\
	"nandboot=run nandargs addip addtty addmtd addmisc;"		\
		"nand read ${kernel_addr_r} kernel\0"			\
		"bootm ${kernel_addr_r}\0"				\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r}\0"				\
	"net_self=if run net_self_load;then "				\
		"run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} ${ramdisk_addr_r};"		\
		"else echo Images not loades;fi\0"			\
	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0"			\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"loadmlo=tftp ${loadaddr} ${mlo}\0"				\
	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0"				\
	"uboot_addr=0x80000\0"						\
	"update=nandecc sw;nand erase ${uboot_addr} 100000;"		\
		"nand write ${loadaddr} ${uboot_addr} 80000\0"		\
	"updatemlo=nandecc hw;nand erase 0 20000;"			\
		"nand write ${loadaddr} 0 20000\0"			\
	"upd=if run load;then echo Updating u-boot;if run update;"	\
		"then echo U-Boot updated;"				\
			"else echo Error updating u-boot !;"		\
			"echo Board without bootloader !!;"		\
		"fi;"							\
		"else echo U-Boot not downloaded..exiting;fi\0"		\

#endif /* __TAM3517_H */
Commit	Line	Data
f9c6fac4 SB	1	/*
	2	* Copyright (C) 2011
	3	* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
	4	*
	5	* Copyright (C) 2009 TechNexion Ltd.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc.
	20	*/
	21
	22	#ifndef __TAM3517_H
	23	#define __TAM3517_H
	24
	25	/*
	26	* High Level Configuration Options
	27	*/
	28	#define CONFIG_OMAP /* in a TI OMAP core */
	29	#define CONFIG_OMAP34XX /* which is a 34XX */
308252ad	30	#define CONFIG_OMAP_GPIO
f9c6fac4 SB	31
	32	#define CONFIG_SYS_TEXT_BASE 0x80008000
	33
	34	#define CONFIG_SYS_CACHELINE_SIZE 64
	35
	36	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	37
	38	#include <asm/arch/cpu.h> /* get chip and board defs */
	39	#include <asm/arch/omap3.h>
	40
	41	/*
	42	* Display CPU and Board information
	43	*/
	44	#define CONFIG_DISPLAY_CPUINFO
	45	#define CONFIG_DISPLAY_BOARDINFO
	46
	47	/* Clock Defines */
	48	#define V_OSCK 26000000 /* Clock output from T2 */
	49	#define V_SCLK (V_OSCK >> 1)
	50
f9c6fac4 SB	51	#define CONFIG_MISC_INIT_R
	52
	53	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	54	#define CONFIG_SETUP_MEMORY_TAGS
	55	#define CONFIG_INITRD_TAG
	56	#define CONFIG_REVISION_TAG
	57
	58	/*
	59	* Size of malloc() pool
	60	*/
	61	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	62	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10) + \
	63	2 * 1024 * 1024)
	64	/*
	65	* DDR related
	66	*/
	67	#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */
	68	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	69
	70	/*
	71	* Hardware drivers
	72	*/
	73
	74	/*
	75	* NS16550 Configuration
	76	*/
	77	#define CONFIG_SYS_NS16550
	78	#define CONFIG_SYS_NS16550_SERIAL
	79	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	80	#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	81
	82	/*
	83	* select serial console configuration
	84	*/
	85	#define CONFIG_CONS_INDEX 1
	86	#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
	87	#define CONFIG_SERIAL1 /* UART1 */
	88
	89	/* allow to overwrite serial and ethaddr */
	90	#define CONFIG_ENV_OVERWRITE
	91	#define CONFIG_BAUDRATE 115200
	92	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	93	115200}
	94	#define CONFIG_MMC
	95	#define CONFIG_OMAP_HSMMC
	96	#define CONFIG_GENERIC_MMC
	97	#define CONFIG_DOS_PARTITION
	98
	99	/* EHCI */
	100	#define CONFIG_OMAP3_GPIO_5
	101	#define CONFIG_USB_EHCI
	102	#define CONFIG_USB_EHCI_OMAP
8c589d6f SB	103	#define CONFIG_USB_ULPI
8c589d6f SB	104	#define CONFIG_USB_ULPI_VIEWPORT_OMAP
f9c6fac4 SB	105	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 25
	106	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
	107	#define CONFIG_USB_STORAGE
	108
	109	/* #define CONFIG_EHCI_DCACHE */
	110
	111	/* commands to include */
	112	#include <config_cmd_default.h>
	113
	114	#define CONFIG_CMD_CACHE
	115	#define CONFIG_CMD_DHCP
	116	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	117	#define CONFIG_CMD_FAT /* FAT support */
	118	#define CONFIG_CMD_GPIO
	119	#define CONFIG_CMD_I2C /* I2C serial bus support */
	120	#define CONFIG_CMD_MII
	121	#define CONFIG_CMD_MMC /* MMC support */
	122	#define CONFIG_CMD_NET
	123	#define CONFIG_CMD_NFS
	124	#define CONFIG_CMD_NAND /* NAND support */
	125	#define CONFIG_CMD_PING
	126	#define CONFIG_CMD_USB
	127
	128	#undef CONFIG_CMD_FLASH /* only NAND on the SOM */
	129	#undef CONFIG_CMD_IMLS
	130
	131	#define CONFIG_SYS_NO_FLASH
	132	#define CONFIG_HARD_I2C
	133	#define CONFIG_SYS_I2C_SPEED 400000
	134	#define CONFIG_SYS_I2C_SLAVE 1
	135	#define CONFIG_SYS_I2C_BUS 0
	136	#define CONFIG_SYS_I2C_BUS_SELECT 1
	137	#define CONFIG_DRIVER_OMAP34XX_I2C
	138
	139
	140	/*
	141	* Board NAND Info.
	142	*/
	143	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	144	/* to access */
	145	/* nand at CS0 */
	146
	147	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	148	/* NAND devices */
f9c6fac4 SB	149
	150	#define CONFIG_AUTO_COMPLETE
	151
	152	/*
	153	* Miscellaneous configurable options
	154	*/
	155	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	156	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
f9c6fac4 SB	157	#define CONFIG_CMDLINE_EDITING
	158	#define CONFIG_AUTO_COMPLETE
	159	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	160
	161	/* Print Buffer Size */
	162	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	163	sizeof(CONFIG_SYS_PROMPT) + 16)
	164	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	165	/* args */
	166	/* Boot Argument Buffer Size */
	167	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	168	/* memtest works on */
	169	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	170	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	171	0x01F00000) /* 31MB */
	172
	173	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	174	/* address */
	175
	176	/*
	177	* AM3517 has 12 GP timers, they can be driven by the system clock
	178	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	179	* This rate is divided by a local divisor.
	180	*/
	181	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	182	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	183	#define CONFIG_SYS_HZ 1000
	184
f9c6fac4 SB	185	/*
	186	* Physical Memory Map
	187	*/
	188	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	189	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	190	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
	191	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	192
	193	/*
	194	* FLASH and environment organization
	195	*/
	196
	197	/* ** PISMO SUPPORT * */
	198
	199	/* Configure the PISMO */
	200	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	201
	202	#define CONFIG_NAND_OMAP_GPMC
	203	#define GPMC_NAND_ECC_LP_x16_LAYOUT
	204	#define CONFIG_ENV_IS_IN_NAND
	205	#define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
	206
	207	/* Redundant Environment */
	208	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	209	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	210	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	211	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
	212	2 * CONFIG_SYS_ENV_SECT_SIZE)
	213	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	214
	215	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	216	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	217	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	218	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	219	CONFIG_SYS_INIT_RAM_SIZE - \
	220	GENERATED_GBL_DATA_SIZE)
	221
	222	/*
	223	* ethernet support, EMAC
	224	*
	225	*/
	226	#define CONFIG_DRIVER_TI_EMAC
	227	#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	228	#define CONFIG_MII
	229	#define CONFIG_EMAC_MDIO_PHY_NUM 0
	230	#define CONFIG_BOOTP_DEFAULT
	231	#define CONFIG_BOOTP_DNS
	232	#define CONFIG_BOOTP_DNS2
	233	#define CONFIG_BOOTP_SEND_HOSTNAME
	234	#define CONFIG_NET_RETRY_COUNT 10
f9c6fac4 SB	235
	236	/* Defines for SPL */
	237	#define CONFIG_SPL
	238	#define CONFIG_SPL_CONSOLE
	239	#define CONFIG_SPL_NAND_SIMPLE
	240	#define CONFIG_SPL_NAND_SOFTECC
	241	#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000 /* below BSS */
	242
	243	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	244	#define CONFIG_SPL_LIBDISK_SUPPORT
	245	#define CONFIG_SPL_I2C_SUPPORT
	246	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	247	#define CONFIG_SPL_SERIAL_SUPPORT
16e41c85	248	#define CONFIG_SPL_GPIO_SUPPORT
f9c6fac4 SB	249	#define CONFIG_SPL_POWER_SUPPORT
	250	#define CONFIG_SPL_NAND_SUPPORT
	251	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	252
	253	#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
e0820ccc	254	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
f9c6fac4 SB	255	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	256
	257	#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	258	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	259	#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	260	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	261
	262	/* NAND boot config */
	263	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	264	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	265	#define CONFIG_SYS_NAND_OOBSIZE 64
	266	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	267	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	268	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	269	#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	270	48, 49, 50, 51, 52, 53, 54, 55,\
	271	56, 57, 58, 59, 60, 61, 62, 63}
	272	#define CONFIG_SYS_NAND_ECCSIZE 256
	273	#define CONFIG_SYS_NAND_ECCBYTES 3
	274
f9c6fac4 SB	275	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	276
	277	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	278	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	279
	280	#define CONFIG_OF_LIBFDT
	281	#define CONFIG_FIT
	282	#define CONFIG_CMD_UBI
	283	#define CONFIG_CMD_UBIFS
	284	#define CONFIG_RBTREE
	285	#define CONFIG_LZO
	286	#define CONFIG_MTD_PARTITIONS
	287	#define CONFIG_MTD_DEVICE
	288	#define CONFIG_CMD_MTDPARTS
	289
	290	/* Setup MTD for NAND on the SOM */
	291	#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
	292	#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \
1fdabedd SB	293	"1m(u-boot),256k(env1)," \
1fdabedd SB	294	"256k(env2),6m(kernel),-(rootfs)"
f9c6fac4 SB	295
	296	#define xstr(s) str(s)
	297	#define str(s) #s
	298
	299	#define CONFIG_TAM3517_SETTINGS \
	300	"netdev=eth0\0" \
	301	"nandargs=setenv bootargs root=${nandroot} " \
	302	"rootfstype=${nandrootfstype}\0" \
	303	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	304	"nfsroot=${serverip}:${rootpath}\0" \
	305	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	306	"addip_sta=setenv bootargs ${bootargs} " \
	307	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	308	":${hostname}:${netdev}:off panic=1\0" \
	309	"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
	310	"addip=if test -n ${ipdyn};then run addip_dyn;" \
	311	"else run addip_sta;fi\0" \
	312	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	313	"addtty=setenv bootargs ${bootargs}" \
	314	" console=ttyO0,${baudrate}\0" \
	315	"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
	316	"loadaddr=82000000\0" \
	317	"kernel_addr_r=82000000\0" \
	318	"hostname=" xstr(CONFIG_HOSTNAME) "\0" \
	319	"bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
	320	"flash_self=run ramargs addip addtty addmtd addmisc;" \
	321	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
	322	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
	323	"bootm ${kernel_addr}\0" \
	324	"nandboot=run nandargs addip addtty addmtd addmisc;" \
	325	"nand read ${kernel_addr_r} kernel\0" \
	326	"bootm ${kernel_addr_r}\0" \
	327	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
	328	"run nfsargs addip addtty addmtd addmisc;" \
	329	"bootm ${kernel_addr_r}\0" \
	330	"net_self=if run net_self_load;then " \
	331	"run ramargs addip addtty addmtd addmisc;" \
	332	"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
	333	"else echo Images not loades;fi\0" \
	334	"u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
	335	"load=tftp ${loadaddr} ${u-boot}\0" \
	336	"loadmlo=tftp ${loadaddr} ${mlo}\0" \
	337	"mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
	338	"uboot_addr=0x80000\0" \
	339	"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
	340	"nand write ${loadaddr} ${uboot_addr} 80000\0" \
	341	"updatemlo=nandecc hw;nand erase 0 20000;" \
	342	"nand write ${loadaddr} 0 20000\0" \
	343	"upd=if run load;then echo Updating u-boot;if run update;" \
	344	"then echo U-Boot updated;" \
	345	"else echo Error updating u-boot !;" \
	346	"echo Board without bootloader !!;" \
	347	"fi;" \
	348	"else echo U-Boot not downloaded..exiting;fi\0" \
	349
	350	#endif /* __TAM3517_H */