[people/ms/u-boot.git] / include / configs / tao3530.h

/*
 * Configuration settings for the TechNexion TAO-3530 SOM
 * equipped on Thunder baseboard.
 *
 * Edward Lin <linuxfae@technexion.com>
 * Tapani Utriainen <linuxfae@technexion.com>
 *
 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap.h>

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(4 << 20)
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/* commands to include */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */

#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED	100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE	1
#define CONFIG_I2C_MULTI_BUS

/*
 * TWL4030
 */
#define CONFIG_TWL4030_LED

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand at */
							/* CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
							/* devices */
/* Environment information */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=600\0" \
	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
	"tv_mode=omapfb.mode=tv:ntsc\0" \
	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
	"extra_options= \0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"${video_mode} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype} " \
		"${extra_options}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"mpurate=${mpurate} " \
		"${video_mode} " \
		"${network_setting} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype} "\
		"${extra_options}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"if mmc rescan ${mmcdev}; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

/* turn on command-line edit/hist/auto */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_ALT_MEMTEST		1
#define CONFIG_SYS_MEMTEST_START	(0x82000000)		/* memtest */
								/* defaults */
#define CONFIG_SYS_MEMTEST_END		(0x83FFFFFF)		/* 64MB */
#define CONFIG_SYS_MEMTEST_SCRATCH	(0x81000000)	/* dummy address */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
							/* load address */
#define CONFIG_SYS_TEXT_BASE		0x80008000

/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */

/*
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
#define CONFIG_SYS_FLASH_BASE		NAND_BASE

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
#define CONFIG_ENV_OFFSET		0x260000
#define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/*
 * USB
 *
 * Currently only EHCI is enabled, the MUSB OTG controller
 * is not enabled.
 */

/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	162

/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
/*
 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 */
#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12, 13 }
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_HAM1_CODE_HW

#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

/*
 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 * older x-loader implementations. And move the BSS area so that it
 * doesn't overlap with TEXT_BASE.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SPL_BSS_START_ADDR	0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#endif /* __CONFIG_H */
Commit	Line	Data
550e3756 TU	1	/*
	2	* Configuration settings for the TechNexion TAO-3530 SOM
	3	* equipped on Thunder baseboard.
	4	*
	5	* Edward Lin <linuxfae@technexion.com>
	6	* Tapani Utriainen <linuxfae@technexion.com>
	7	*
a9f52490 SR	8	* Copyright (C) 2013 Stefan Roese <sr@denx.de>
a9f52490 SR	9	*
550e3756 TU	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
550e3756	19
550e3756	20	#include <asm/arch/cpu.h> /* get chip and board defs */
987ec585	21	#include <asm/arch/omap.h>
550e3756	22
550e3756 TU	23	/* Clock Defines */
	24	#define V_OSCK 26000000 /* Clock output from T2 */
	25	#define V_SCLK (V_OSCK >> 1)
	26
	27	#define CONFIG_MISC_INIT_R
	28
550e3756 TU	29	#define CONFIG_CMDLINE_TAG
	30	#define CONFIG_SETUP_MEMORY_TAGS
	31	#define CONFIG_INITRD_TAG
	32	#define CONFIG_REVISION_TAG
	33
	34	/*
	35	* Size of malloc() pool
	36	*/
	37	#define CONFIG_SYS_MALLOC_LEN (4 << 20)
	38	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	39
	40	/*
	41	* Hardware drivers
	42	*/
	43
	44	/*
	45	* NS16550 Configuration
	46	*/
	47	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	48
550e3756 TU	49	#define CONFIG_SYS_NS16550_SERIAL
	50	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	51	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	52
	53	/*
	54	* select serial console configuration
	55	*/
	56	#define CONFIG_CONS_INDEX 3
	57	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	58
	59	/* allow to overwrite serial and ethaddr */
	60	#define CONFIG_ENV_OVERWRITE
550e3756 TU	61
550e3756 TU	62	/* commands to include */
550e3756	63	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
550e3756	64
550e3756	65	#define CONFIG_SYS_I2C
550e3756 TU	66	#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
	67	#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
	68	#define CONFIG_I2C_MULTI_BUS
	69
	70	/*
	71	* TWL4030
	72	*/
550e3756 TU	73	#define CONFIG_TWL4030_LED
	74
	75	/*
	76	* Board NAND Info.
	77	*/
550e3756 TU	78	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	79	/* to access nand */
	80	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	81	/* to access nand at */
	82	/* CS0 */
550e3756 TU	83
	84	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	85	/* devices */
	86	/* Environment information */
550e3756 TU	87
	88	#define CONFIG_EXTRA_ENV_SETTINGS \
	89	"loadaddr=0x82000000\0" \
	90	"console=ttyO2,115200n8\0" \
	91	"mpurate=600\0" \
	92	"dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
	93	"tv_mode=omapfb.mode=tv:ntsc\0" \
	94	"video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
	95	"lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
	96	"extra_options= \0" \
550e3756 TU	97	"mmcdev=0\0" \
	98	"mmcroot=/dev/mmcblk0p2 rw\0" \
	99	"mmcrootfstype=ext3 rootwait\0" \
	100	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
	101	"nandrootfstype=ubifs\0" \
	102	"mmcargs=setenv bootargs console=${console} " \
550e3756 TU	103	"mpurate=${mpurate} " \
	104	"${video_mode} " \
	105	"root=${mmcroot} " \
	106	"rootfstype=${mmcrootfstype} " \
	107	"${extra_options}\0" \
	108	"nandargs=setenv bootargs console=${console} " \
550e3756 TU	109	"mpurate=${mpurate} " \
	110	"${video_mode} " \
	111	"${network_setting} " \
	112	"root=${nandroot} " \
	113	"rootfstype=${nandrootfstype} "\
	114	"${extra_options}\0" \
	115	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	116	"bootscript=echo Running bootscript from mmc ...; " \
	117	"source ${loadaddr}\0" \
	118	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	119	"mmcboot=echo Booting from mmc ...; " \
	120	"run mmcargs; " \
	121	"bootm ${loadaddr}\0" \
	122	"nandboot=echo Booting from nand ...; " \
	123	"run nandargs; " \
	124	"nand read ${loadaddr} 280000 400000; " \
	125	"bootm ${loadaddr}\0" \
	126
	127	#define CONFIG_BOOTCOMMAND \
	128	"if mmc rescan ${mmcdev}; then " \
	129	"if run loadbootscript; then " \
	130	"run bootscript; " \
	131	"else " \
	132	"if run loaduimage; then " \
	133	"run mmcboot; " \
	134	"else run nandboot; " \
	135	"fi; " \
	136	"fi; " \
	137	"else run nandboot; fi"
	138
	139	/*
	140	* Miscellaneous configurable options
	141	*/
	142	#define CONFIG_SYS_LONGHELP /* undef to save memory */
550e3756 TU	143
	144	/* turn on command-line edit/hist/auto */
	145	#define CONFIG_CMDLINE_EDITING
550e3756 TU	146	#define CONFIG_AUTO_COMPLETE
550e3756 TU	147
550e3756 TU	148	#define CONFIG_SYS_ALT_MEMTEST 1
	149	#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
	150	/* defaults */
	151	#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
	152	#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
	153
	154	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
	155	/* load address */
	156	#define CONFIG_SYS_TEXT_BASE 0x80008000
	157
	158	/*
	159	* OMAP3 has 12 GP timers, they can be driven by the system clock
	160	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	161	* This rate is divided by a local divisor.
	162	*/
	163	#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
	164	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	165
550e3756 TU	166	/*
	167	* Physical Memory Map
	168	*/
	169	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	170	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	171	#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
	172	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	173
	174	/*
	175	* FLASH and environment organization
	176	*/
	177
	178	/* ** PISMO SUPPORT * */
550e3756	179	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
222a3113	180	#define CONFIG_SYS_FLASH_BASE NAND_BASE
550e3756 TU	181
	182	/* Monitor at start of flash */
	183	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	184	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	185
550e3756	186	#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
550e3756 TU	187
550e3756 TU	188	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
7672d9d5	189	#define CONFIG_ENV_OFFSET 0x260000
550e3756 TU	190	#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
	191
	192	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	193	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	194	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	195	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	196	CONFIG_SYS_INIT_RAM_SIZE - \
	197	GENERATED_GBL_DATA_SIZE)
	198
550e3756 TU	199	/*
	200	* USB
	201	*
	202	* Currently only EHCI is enabled, the MUSB OTG controller
	203	* is not enabled.
	204	*/
	205
	206	/* USB EHCI */
550e3756 TU	207	#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
550e3756 TU	208
a9f52490	209	/* Defines for SPL */
a9f52490	210	#define CONFIG_SPL_FRAMEWORK
a9f52490	211
e2ccdf89	212	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	213	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
a9f52490	214
a9f52490 SR	215	#define CONFIG_SPL_NAND_BASE
	216	#define CONFIG_SPL_NAND_DRIVERS
	217	#define CONFIG_SPL_NAND_ECC
a9f52490 SR	218
	219	/* NAND boot config */
	220	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	221	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	222	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	223	#define CONFIG_SYS_NAND_OOBSIZE 64
	224	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
	225	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	226	/*
	227	* Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
	228	* SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
	229	*/
	230	#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
	231	10, 11, 12, 13 }
	232	#define CONFIG_SYS_NAND_ECCSIZE 512
	233	#define CONFIG_SYS_NAND_ECCBYTES 3
	234	#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
	235
	236	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	237	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	238
	239	#define CONFIG_SPL_TEXT_BASE 0x40200800
fa2f81b0 TR	240	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	241	CONFIG_SPL_TEXT_BASE)
a9f52490 SR	242
	243	/*
	244	* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
	245	* older x-loader implementations. And move the BSS area so that it
	246	* doesn't overlap with TEXT_BASE.
	247	*/
	248	#define CONFIG_SYS_TEXT_BASE 0x80008000
	249	#define CONFIG_SPL_BSS_START_ADDR 0x80100000
	250	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	251
	252	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	253	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	254
550e3756	255	#endif /* __CONFIG_H */