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1/*
2 * Copyright (C) 2014 Soeren Moch <smoch@web.de>
3 *
4 * Configuration settings for the TBS2910 MatrixARM board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __TBS2910_CONFIG_H
10#define __TBS2910_CONFIG_H
11
12#include "mx6_common.h"
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13
14/* General configuration */
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15#define CONFIG_SYS_THUMB_BUILD
16
17#define CONFIG_MACH_TYPE 3980
18
05d492a3 19#define CONFIG_BOARD_EARLY_INIT_F
05d492a3 20
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21#define CONFIG_SYS_HZ 1000
22
1368f993 23#define CONFIG_IMX_THERMAL
fbd18aa6 24
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25/* Physical Memory Map */
26#define CONFIG_NR_DRAM_BANKS 1
27#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR
28
29#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
30#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
31#define CONFIG_SYS_INIT_SP_OFFSET \
32 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
33#define CONFIG_SYS_INIT_SP_ADDR \
34 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
35
36#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
37
38#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
39#define CONFIG_SYS_MEMTEST_END \
40 (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
41
05d492a3 42#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
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43
44/* Serial console */
45#define CONFIG_MXC_UART
46#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */
47#define CONFIG_BAUDRATE 115200
48
49#define CONFIG_SYS_CONSOLE_IS_IN_ENV
50#define CONFIG_CONSOLE_MUX
51#define CONFIG_CONS_INDEX 1
52
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53#define CONFIG_PRE_CONSOLE_BUFFER
54#define CONFIG_PRE_CON_BUF_SZ 4096
55#define CONFIG_PRE_CON_BUF_ADDR 0x7C000000
56
05d492a3 57/* *** Command definition *** */
05d492a3 58#define CONFIG_CMD_BMODE
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59
60/* Filesystems / image support */
05d492a3 61#define CONFIG_EFI_PARTITION
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62
63/* MMC */
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64#define CONFIG_SYS_FSL_USDHC_NUM 3
65#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
9927d60f 66#define CONFIG_SUPPORT_EMMC_BOOT
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67
68/* Ethernet */
69#define CONFIG_FEC_MXC
05d492a3 70#define CONFIG_CMD_MII
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71#define CONFIG_FEC_MXC
72#define CONFIG_MII
73#define IMX_FEC_BASE ENET_BASE_ADDR
74#define CONFIG_FEC_XCV_TYPE RGMII
75#define CONFIG_ETHPRIME "FEC"
76#define CONFIG_FEC_MXC_PHYADDR 4
77#define CONFIG_PHYLIB
78#define CONFIG_PHY_ATHEROS
79
80/* Framebuffer */
81#define CONFIG_VIDEO
82#ifdef CONFIG_VIDEO
83#define CONFIG_VIDEO_IPUV3
84#define CONFIG_IPUV3_CLK 260000000
85#define CONFIG_CFB_CONSOLE
86#define CONFIG_CFB_CONSOLE_ANSI
87#define CONFIG_VIDEO_SW_CURSOR
88#define CONFIG_VGA_AS_SINGLE_DEVICE
89#define CONFIG_VIDEO_BMP_RLE8
90#define CONFIG_IMX_HDMI
91#define CONFIG_IMX_VIDEO_SKIP
92#define CONFIG_CMD_HDMIDETECT
93#endif
94
95/* PCI */
96#define CONFIG_CMD_PCI
97#ifdef CONFIG_CMD_PCI
98#define CONFIG_PCI
99#define CONFIG_PCI_PNP
100#define CONFIG_PCI_SCAN_SHOW
101#define CONFIG_PCIE_IMX
102#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12)
103#endif
104
105/* SATA */
106#define CONFIG_CMD_SATA
107#ifdef CONFIG_CMD_SATA
108#define CONFIG_DWC_AHSATA
109#define CONFIG_SYS_SATA_MAX_DEVICE 1
110#define CONFIG_DWC_AHSATA_PORT_ID 0
111#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
112#define CONFIG_LBA48
113#define CONFIG_LIBATA
114#endif
115
116/* USB */
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117#ifdef CONFIG_CMD_USB
118#define CONFIG_USB_EHCI
119#define CONFIG_USB_EHCI_MX6
120#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
d896276d 121#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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122#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
123#define CONFIG_USB_STORAGE
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124#define CONFIG_CMD_USB_MASS_STORAGE
125#ifdef CONFIG_CMD_USB_MASS_STORAGE
6628aa57 126#define CONFIG_USBD_HS
01acd6ab 127#define CONFIG_USB_FUNCTION_MASS_STORAGE
6628aa57 128#endif /* CONFIG_CMD_USB_MASS_STORAGE */
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129#define CONFIG_USB_KEYBOARD
130#ifdef CONFIG_USB_KEYBOARD
daa12e3f 131#define CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE
05d492a3 132#define CONFIG_SYS_STDIO_DEREGISTER
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133#define CONFIG_PREBOOT \
134 "if hdmidet; then " \
135 "usb start; " \
136 "run set_con_usb_hdmi; " \
137 "else " \
138 "run set_con_serial; " \
139 "fi;"
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140#endif /* CONFIG_USB_KEYBOARD */
141#endif /* CONFIG_CMD_USB */
142
143/* RTC */
144#define CONFIG_CMD_DATE
145#ifdef CONFIG_CMD_DATE
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146#define CONFIG_RTC_DS1307
147#define CONFIG_SYS_RTC_BUS_NUM 2
148#endif
149
150/* I2C */
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151#ifdef CONFIG_CMD_I2C
152#define CONFIG_SYS_I2C
153#define CONFIG_SYS_I2C_MXC
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154#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
155#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
f8cb101e 156#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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157#define CONFIG_SYS_I2C_SPEED 100000
158#define CONFIG_I2C_EDID
159#endif
160
056845c2 161/* Environment organization */
05d492a3 162#define CONFIG_ENV_IS_IN_MMC
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163#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */
164#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */
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165#define CONFIG_ENV_SIZE (8 * 1024)
166#define CONFIG_ENV_OFFSET (384 * 1024)
167#define CONFIG_ENV_OVERWRITE
168
169#define CONFIG_EXTRA_ENV_SETTINGS \
170 "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \
171 "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \
172 "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \
173 "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \
174 "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \
175 "${bootargs_mmc3}\0" \
176 "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \
177 "rdinit=/sbin/init enable_wait_mode=off\0" \
178 "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \
b9a16099 179 "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \
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180 "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \
181 "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \
182 "run bootargs_upd; " \
183 "bootm 0x10800000 0x10d00000\0" \
184 "console=ttymxc0\0" \
185 "fan=gpio set 92\0" \
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186 "set_con_serial=setenv stdin serial; " \
187 "setenv stdout serial; " \
188 "setenv stderr serial;\0" \
189 "set_con_usb_hdmi=setenv stdin serial,usbkbd; " \
190 "setenv stdout serial,vga; " \
191 "setenv stderr serial,vga;\0"
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192
193#define CONFIG_BOOTCOMMAND \
194 "mmc rescan; " \
195 "if run bootcmd_up1; then " \
196 "run bootcmd_up2; " \
197 "else " \
198 "run bootcmd_mmc; " \
199 "fi"
200
201#endif /* __TBS2910_CONFIG_H * */