[people/ms/u-boot.git] / include / configs / tegra124-common.h

/*
 * (C) Copyright 2013
 * NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef _TEGRA124_COMMON_H_
#define _TEGRA124_COMMON_H_

#include "tegra-common.h"

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_STACKBASE	0x82800000	/* 40MB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */

/*
 * Memory layout for where various images get loaded by boot scripts:
 *
 * scriptaddr can be pretty much anywhere that doesn't conflict with something
 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * kernel_addr_r must be within the first 128M of RAM in order for the
 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
 *   should not overlap that area, or the kernel will have to copy itself
 *   somewhere else before decompression. Similarly, the address of any other
 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
 *   this up to 16M allows for a sizable kernel to be decompressed below the
 *   compressed load address.
 *
 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
 *   the compressed kernel to be up to 16M too.
 *
 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
 */
#define CONFIG_LOADADDR 0x81000000
#define MEM_LAYOUT_ENV_SETTINGS \
	"scriptaddr=0x90000000\0" \
	"pxefile_addr_r=0x90100000\0" \
	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	"fdt_addr_r=0x82000000\0" \
	"ramdisk_addr_r=0x82100000\0"

/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x80108000
#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
#define CONFIG_SPL_STACK		0x800ffffc

/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10

/* GPU needs setup */
#define CONFIG_TEGRA_GPU

#endif /* _TEGRA124_COMMON_H_ */
Commit	Line	Data
f7dc4ac3 TW	1	/*
	2	* (C) Copyright 2013
	3	* NVIDIA Corporation <www.nvidia.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#ifndef _TEGRA124_COMMON_H_
	9	#define _TEGRA124_COMMON_H_
	10
	11	#include "tegra-common.h"
	12
f7dc4ac3 TW	13	/*
	14	* NS16550 Configuration
	15	*/
	16	#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
	17
f7dc4ac3 TW	18	/*
	19	* Miscellaneous configurable options
	20	*/
f7dc4ac3 TW	21	#define CONFIG_STACKBASE 0x82800000 /* 40MB */
	22
	23	/*-----------------------------------------------------------------------
	24	* Physical Memory Map
	25	*/
f7dc4ac3 TW	26
	27	/*
	28	* Memory layout for where various images get loaded by boot scripts:
	29	*
	30	* scriptaddr can be pretty much anywhere that doesn't conflict with something
	31	* else. Put it above BOOTMAPSZ to eliminate conflicts.
	32	*
	33	* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
	34	* something else. Put it above BOOTMAPSZ to eliminate conflicts.
	35	*
	36	* kernel_addr_r must be within the first 128M of RAM in order for the
	37	* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
	38	* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
	39	* should not overlap that area, or the kernel will have to copy itself
	40	* somewhere else before decompression. Similarly, the address of any other
	41	* data passed to the kernel shouldn't overlap the start of RAM. Pushing
	42	* this up to 16M allows for a sizable kernel to be decompressed below the
	43	* compressed load address.
	44	*
	45	* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
	46	* the compressed kernel to be up to 16M too.
	47	*
	48	* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
	49	* for the FDT/DTB to be up to 1M, which is hopefully plenty.
	50	*/
48cfca24	51	#define CONFIG_LOADADDR 0x81000000
f7dc4ac3 TW	52	#define MEM_LAYOUT_ENV_SETTINGS \
	53	"scriptaddr=0x90000000\0" \
	54	"pxefile_addr_r=0x90100000\0" \
48cfca24	55	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
f7dc4ac3 TW	56	"fdt_addr_r=0x82000000\0" \
	57	"ramdisk_addr_r=0x82100000\0"
	58
	59	/* Defines for SPL */
	60	#define CONFIG_SPL_TEXT_BASE 0x80108000
	61	#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
	62	#define CONFIG_SPL_STACK 0x800ffffc
	63
f7dc4ac3 TW	64	/* For USB EHCI controller */
f7dc4ac3 TW	65	#define CONFIG_EHCI_IS_TDI
7bc5c8c9	66	#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
f7dc4ac3	67
871d78ed AC	68	/* GPU needs setup */
	69	#define CONFIG_TEGRA_GPU
	70
f7dc4ac3	71	#endif /* _TEGRA124_COMMON_H_ */