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efc05ae1 | 1 | /* |
52a8b820 | 2 | * (C) Copyright 2010-2012 |
efc05ae1 TW |
3 | * NVIDIA Corporation <www.nvidia.com> |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
efc05ae1 TW |
6 | */ |
7 | ||
f01b631f TW |
8 | #ifndef _TEGRA20_COMMON_H_ |
9 | #define _TEGRA20_COMMON_H_ | |
10 | #include "tegra-common.h" | |
11 | ||
0d79f4f4 TR |
12 | /* Cortex-A9 uses a cache line size of 32 bytes */ |
13 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
14 | ||
c44bb3a3 SW |
15 | /* |
16 | * Errata configuration | |
17 | */ | |
53612132 | 18 | #define CONFIG_ARM_ERRATA_716044 |
c44bb3a3 SW |
19 | #define CONFIG_ARM_ERRATA_742230 |
20 | #define CONFIG_ARM_ERRATA_751472 | |
21 | ||
f01b631f TW |
22 | /* |
23 | * NS16550 Configuration | |
24 | */ | |
25 | #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ | |
649d0ffb | 26 | |
f01b631f TW |
27 | /* Environment information, boards can override if required */ |
28 | #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ | |
96d21237 | 29 | |
f01b631f TW |
30 | /* |
31 | * Miscellaneous configurable options | |
32 | */ | |
33 | #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ | |
34 | #define CONFIG_STACKBASE 0x02800000 /* 40MB */ | |
efc05ae1 | 35 | |
f01b631f TW |
36 | /*----------------------------------------------------------------------- |
37 | * Physical Memory Map | |
38 | */ | |
39 | #define CONFIG_SYS_TEXT_BASE 0x0010E000 | |
ad16617f | 40 | |
efc05ae1 | 41 | /* |
f01b631f TW |
42 | * Memory layout for where various images get loaded by boot scripts: |
43 | * | |
44 | * scriptaddr can be pretty much anywhere that doesn't conflict with something | |
45 | * else. Put it above BOOTMAPSZ to eliminate conflicts. | |
46 | * | |
f940c72e SW |
47 | * pxefile_addr_r can be pretty much anywhere that doesn't conflict with |
48 | * something else. Put it above BOOTMAPSZ to eliminate conflicts. | |
49 | * | |
f01b631f TW |
50 | * kernel_addr_r must be within the first 128M of RAM in order for the |
51 | * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will | |
52 | * decompress itself to 0x8000 after the start of RAM, kernel_addr_r | |
53 | * should not overlap that area, or the kernel will have to copy itself | |
54 | * somewhere else before decompression. Similarly, the address of any other | |
55 | * data passed to the kernel shouldn't overlap the start of RAM. Pushing | |
56 | * this up to 16M allows for a sizable kernel to be decompressed below the | |
57 | * compressed load address. | |
58 | * | |
59 | * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for | |
60 | * the compressed kernel to be up to 16M too. | |
61 | * | |
62 | * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows | |
63 | * for the FDT/DTB to be up to 1M, which is hopefully plenty. | |
efc05ae1 | 64 | */ |
f01b631f TW |
65 | #define MEM_LAYOUT_ENV_SETTINGS \ |
66 | "scriptaddr=0x10000000\0" \ | |
f940c72e | 67 | "pxefile_addr_r=0x10100000\0" \ |
f01b631f TW |
68 | "kernel_addr_r=0x01000000\0" \ |
69 | "fdt_addr_r=0x02000000\0" \ | |
70 | "ramdisk_addr_r=0x02100000\0" | |
efc05ae1 | 71 | |
f01b631f TW |
72 | /* Defines for SPL */ |
73 | #define CONFIG_SPL_TEXT_BASE 0x00108000 | |
74 | #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 | |
75 | #define CONFIG_SPL_STACK 0x000ffffc | |
76 | ||
f01b631f TW |
77 | /* Align LCD to 1MB boundary */ |
78 | #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE | |
efc05ae1 | 79 | |
29f3e3f2 | 80 | #ifdef CONFIG_TEGRA_LP0 |
649d0ffb SG |
81 | #define TEGRA_LP0_ADDR 0x1C406000 |
82 | #define TEGRA_LP0_SIZE 0x2000 | |
83 | #define TEGRA_LP0_VEC \ | |
f01b631f | 84 | "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ |
51926d5e | 85 | "@" __stringify(TEGRA_LP0_ADDR) " " |
649d0ffb SG |
86 | #else |
87 | #define TEGRA_LP0_VEC | |
88 | #endif | |
89 | ||
0291091c SG |
90 | /* |
91 | * This parameter affects a TXFILLTUNING field that controls how much data is | |
92 | * sent to the latency fifo before it is sent to the wire. Without this | |
93 | * parameter, the default (2) causes occasional Data Buffer Errors in OUT | |
94 | * packets depending on the buffer address and size. | |
95 | */ | |
96 | #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 | |
97 | #define CONFIG_EHCI_IS_TDI | |
f75dc784 | 98 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 |
0291091c | 99 | |
0dd84084 | 100 | #define CONFIG_SYS_NAND_SELF_INIT |
a833b950 | 101 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
0dd84084 | 102 | |
f01b631f | 103 | #endif /* _TEGRA20_COMMON_H_ */ |