[people/ms/u-boot.git] / include / configs / tegra20-common.h

/*
 *  (C) Copyright 2010-2012
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _TEGRA20_COMMON_H_
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"

/*
 * Errata configuration
 */
#define CONFIG_ARM_ERRATA_716044
#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_751472

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_STACKBASE	0x02800000	/* 40MB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_SYS_TEXT_BASE	0x00110000

/*
 * Memory layout for where various images get loaded by boot scripts:
 *
 * scriptaddr can be pretty much anywhere that doesn't conflict with something
 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * kernel_addr_r must be within the first 128M of RAM in order for the
 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
 *   should not overlap that area, or the kernel will have to copy itself
 *   somewhere else before decompression. Similarly, the address of any other
 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
 *   this up to 16M allows for a sizable kernel to be decompressed below the
 *   compressed load address.
 *
 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
 *   the compressed kernel to be up to 16M too.
 *
 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
 */
#define CONFIG_LOADADDR 0x01000000
#define MEM_LAYOUT_ENV_SETTINGS \
	"scriptaddr=0x10000000\0" \
	"pxefile_addr_r=0x10100000\0" \
	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
	"fdt_addr_r=0x02000000\0" \
	"ramdisk_addr_r=0x02100000\0"

/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x00108000
#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
#define CONFIG_SPL_STACK		0x000ffffc

/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE

#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR			0x1C406000
#define TEGRA_LP0_SIZE			0x2000
#define TEGRA_LP0_VEC \
	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
	"@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif

/*
 * This parameter affects a TXFILLTUNING field that controls how much data is
 * sent to the latency fifo before it is sent to the wire. Without this
 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
 * packets depending on the buffer address and size.
 */
#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
#define CONFIG_EHCI_IS_TDI
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1

#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION

#endif /* _TEGRA20_COMMON_H_ */
Commit	Line	Data
efc05ae1	1	/*
52a8b820	2	* (C) Copyright 2010-2012
efc05ae1 TW	3	* NVIDIA Corporation <www.nvidia.com>
efc05ae1 TW	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
efc05ae1 TW	6	*/
efc05ae1 TW	7
f01b631f TW	8	#ifndef _TEGRA20_COMMON_H_
	9	#define _TEGRA20_COMMON_H_
	10	#include "tegra-common.h"
	11
c44bb3a3 SW	12	/*
	13	* Errata configuration
	14	*/
53612132	15	#define CONFIG_ARM_ERRATA_716044
c44bb3a3 SW	16	#define CONFIG_ARM_ERRATA_742230
	17	#define CONFIG_ARM_ERRATA_751472
	18
f01b631f TW	19	/*
	20	* NS16550 Configuration
	21	*/
	22	#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
649d0ffb	23
f01b631f TW	24	/*
	25	* Miscellaneous configurable options
	26	*/
f01b631f	27	#define CONFIG_STACKBASE 0x02800000 /* 40MB */
efc05ae1	28
f01b631f TW	29	/*-----------------------------------------------------------------------
	30	* Physical Memory Map
	31	*/
930c514d	32	#define CONFIG_SYS_TEXT_BASE 0x00110000
ad16617f	33
efc05ae1	34	/*
f01b631f TW	35	* Memory layout for where various images get loaded by boot scripts:
	36	*
	37	* scriptaddr can be pretty much anywhere that doesn't conflict with something
	38	* else. Put it above BOOTMAPSZ to eliminate conflicts.
	39	*
f940c72e SW	40	* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
	41	* something else. Put it above BOOTMAPSZ to eliminate conflicts.
	42	*
f01b631f TW	43	* kernel_addr_r must be within the first 128M of RAM in order for the
	44	* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
	45	* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
	46	* should not overlap that area, or the kernel will have to copy itself
	47	* somewhere else before decompression. Similarly, the address of any other
	48	* data passed to the kernel shouldn't overlap the start of RAM. Pushing
	49	* this up to 16M allows for a sizable kernel to be decompressed below the
	50	* compressed load address.
	51	*
	52	* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
	53	* the compressed kernel to be up to 16M too.
	54	*
	55	* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
	56	* for the FDT/DTB to be up to 1M, which is hopefully plenty.
efc05ae1	57	*/
48cfca24	58	#define CONFIG_LOADADDR 0x01000000
f01b631f TW	59	#define MEM_LAYOUT_ENV_SETTINGS \
f01b631f TW	60	"scriptaddr=0x10000000\0" \
f940c72e	61	"pxefile_addr_r=0x10100000\0" \
48cfca24	62	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
f01b631f TW	63	"fdt_addr_r=0x02000000\0" \
f01b631f TW	64	"ramdisk_addr_r=0x02100000\0"
efc05ae1	65
f01b631f TW	66	/* Defines for SPL */
	67	#define CONFIG_SPL_TEXT_BASE 0x00108000
	68	#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
	69	#define CONFIG_SPL_STACK 0x000ffffc
	70
f01b631f TW	71	/* Align LCD to 1MB boundary */
f01b631f TW	72	#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
efc05ae1	73
29f3e3f2	74	#ifdef CONFIG_TEGRA_LP0
649d0ffb SG	75	#define TEGRA_LP0_ADDR 0x1C406000
	76	#define TEGRA_LP0_SIZE 0x2000
	77	#define TEGRA_LP0_VEC \
f01b631f	78	"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
51926d5e	79	"@" __stringify(TEGRA_LP0_ADDR) " "
649d0ffb SG	80	#else
	81	#define TEGRA_LP0_VEC
	82	#endif
	83
0291091c SG	84	/*
	85	* This parameter affects a TXFILLTUNING field that controls how much data is
	86	* sent to the latency fifo before it is sent to the wire. Without this
	87	* parameter, the default (2) causes occasional Data Buffer Errors in OUT
	88	* packets depending on the buffer address and size.
	89	*/
	90	#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
	91	#define CONFIG_EHCI_IS_TDI
f75dc784	92	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
0291091c	93
0dd84084	94	#define CONFIG_SYS_NAND_SELF_INIT
a833b950	95	#define CONFIG_SYS_NAND_ONFI_DETECTION
0dd84084	96
f01b631f	97	#endif /* _TEGRA20_COMMON_H_ */