[people/ms/u-boot.git] / include / configs / theadorable.h

/*
 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_THEADORABLE_H
#define _CONFIG_THEADORABLE_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define	CONFIG_SYS_TEXT_BASE	0x00800000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SATA

/*
 * The debugging version enables USB support via defconfig.
 * This version should also enable all other non-production
 * interfaces / features.
 */
#ifdef CONFIG_USB
#define CONFIG_CMD_PCI
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT

/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"fdt_high=0x10000000\0"		\
	"initrd_high=0x10000000\0"

/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_SATA_MV
#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_EFI_PARTITION
#define CONFIG_DOS_PARTITION

/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT

/* PCIe support */
#ifdef CONFIG_CMD_PCI
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_MVEBU
#endif
#endif

/* Enable LCD and reserve 512KB from top of memory*/
#define CONFIG_SYS_MEM_TOP_HIDE		0x80000

#define CONFIG_CMD_BMP

/* FPGA programming support */
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_STRATIX_V

/*
 * Bootcounter
 */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_RAM
/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
#define BOOTCOUNT_ADDR			0x1000

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */

#endif /* _CONFIG_THEADORABLE_H */
Commit	Line	Data
b20c38a9 SR	1	/*
	2	* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_THEADORABLE_H
	8	#define _CONFIG_THEADORABLE_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_DISPLAY_BOARDINFO_LATE
	14
	15	/*
	16	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	17	* for DDR ECC byte filling in the SPL before loading the main
	18	* U-Boot into it.
	19	*/
	20	#define CONFIG_SYS_TEXT_BASE 0x00800000
	21	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	22
	23	/*
	24	* Commands configuration
	25	*/
b20c38a9	26	#define CONFIG_CMD_ENV
b20c38a9	27	#define CONFIG_CMD_SATA
b20c38a9 SR	28
	29	/*
	30	* The debugging version enables USB support via defconfig.
	31	* This version should also enable all other non-production
	32	* interfaces / features.
	33	*/
	34	#ifdef CONFIG_USB
b20c38a9	35	#define CONFIG_CMD_PCI
b20c38a9 SR	36	#endif
	37
	38	/* I2C */
	39	#define CONFIG_SYS_I2C
	40	#define CONFIG_SYS_I2C_MVTWSI
	41	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
8ac71da9	42	#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
b20c38a9 SR	43	#define CONFIG_SYS_I2C_SLAVE 0x0
	44	#define CONFIG_SYS_I2C_SPEED 100000
	45
	46	/* USB/EHCI configuration */
	47	#define CONFIG_EHCI_IS_TDI
	48	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
	49
	50	#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
	51
	52	/* SPI NOR flash default params, used by sf commands */
	53	#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
	54	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	55
	56	/* Environment in SPI NOR flash */
	57	#define CONFIG_ENV_IS_IN_SPI_FLASH
	58	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	59	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	60	#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
	61	#define CONFIG_ENV_OVERWRITE
	62
	63	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
	64	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	65
b20c38a9 SR	66	#define CONFIG_SYS_ALT_MEMTEST
b20c38a9 SR	67	#define CONFIG_PREBOOT
b20c38a9	68
b20c38a9 SR	69	/* Keep device tree and initrd in lower memory so the kernel can access them */
	70	#define CONFIG_EXTRA_ENV_SETTINGS \
	71	"fdt_high=0x10000000\0" \
	72	"initrd_high=0x10000000\0"
	73
	74	/* SATA support */
	75	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	76	#define CONFIG_SATA_MV
	77	#define CONFIG_LIBATA
	78	#define CONFIG_LBA48
	79	#define CONFIG_EFI_PARTITION
	80	#define CONFIG_DOS_PARTITION
	81
	82	/* Additional FS support/configuration */
	83	#define CONFIG_SUPPORT_VFAT
	84
	85	/* PCIe support */
	86	#ifdef CONFIG_CMD_PCI
	87	#ifndef CONFIG_SPL_BUILD
b20c38a9	88	#define CONFIG_PCI_MVEBU
b20c38a9 SR	89	#endif
	90	#endif
	91
	92	/* Enable LCD and reserve 512KB from top of memory*/
	93	#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
	94
b20c38a9 SR	95	#define CONFIG_CMD_BMP
b20c38a9 SR	96
aea02abe SR	97	/* FPGA programming support */
	98	#define CONFIG_FPGA
	99	#define CONFIG_FPGA_ALTERA
	100	#define CONFIG_FPGA_STRATIX_V
	101
28226b9a SR	102	/*
	103	* Bootcounter
	104	*/
	105	#define CONFIG_BOOTCOUNT_LIMIT
	106	#define CONFIG_BOOTCOUNT_RAM
	107	/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
	108	#define BOOTCOUNT_ADDR 0x1000
	109
b20c38a9 SR	110	/*
	111	* mv-common.h should be defined after CMD configs since it used them
	112	* to enable certain macros
	113	*/
	114	#include "mv-common.h"
	115
	116	/*
	117	* Memory layout while starting into the bin_hdr via the
	118	* BootROM:
	119	*
	120	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	121	* 0x4000.4030 bin_hdr start address
	122	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	123	* 0x4007.fffc BootROM stack top
	124	*
	125	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	126	* L2 cache thus cannot be used.
	127	*/
	128
	129	/* SPL */
	130	/* Defines for SPL */
	131	#define CONFIG_SPL_FRAMEWORK
	132	#define CONFIG_SPL_TEXT_BASE 0x40004030
	133	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	134
	135	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	136	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	137
	138	#ifdef CONFIG_SPL_BUILD
	139	#define CONFIG_SYS_MALLOC_SIMPLE
	140	#endif
	141
	142	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	143	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	144
b20c38a9	145	/* SPL related SPI defines */
b20c38a9	146	#define CONFIG_SPL_SPI_LOAD
b20c38a9 SR	147	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
	148	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
	149
	150	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
	151	#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
	152
	153	#endif /* _CONFIG_THEADORABLE_H */