[people/ms/u-boot.git] / include / configs / theadorable.h

/*
 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_THEADORABLE_H
#define _CONFIG_THEADORABLE_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define	CONFIG_SYS_TEXT_BASE	0x00800000
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SATA
#define CONFIG_CMD_TIME

/*
 * The debugging version enables USB support via defconfig.
 * This version should also enable all other non-production
 * interfaces / features.
 */
#ifdef CONFIG_USB
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_TFTPPUT
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

/* Environment in SPI NOR flash */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT


/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"fdt_high=0x10000000\0"		\
	"initrd_high=0x10000000\0"

/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_SATA_MV
#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_EFI_PARTITION
#define CONFIG_DOS_PARTITION

/* Additional FS support/configuration */
#define CONFIG_SUPPORT_VFAT

/* PCIe support */
#ifdef CONFIG_CMD_PCI
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI
#define CONFIG_PCI_MVEBU
#define CONFIG_PCI_PNP
#define CONFIG_BOARD_LATE_INIT		/* for PEX switch test */
#endif
#endif

/* Enable LCD and reserve 512KB from top of memory*/
#define CONFIG_SYS_MEM_TOP_HIDE		0x80000

#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP

/* FPGA programming support */
#define CONFIG_FPGA
#define CONFIG_FPGA_ALTERA
#define CONFIG_FPGA_STRATIX_V

/*
 * Bootcounter
 */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_BOOTCOUNT_RAM
/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
#define BOOTCOUNT_ADDR			0x1000

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_BUS		0
#define CONFIG_SPL_SPI_CS		0
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */

#endif /* _CONFIG_THEADORABLE_H */
Commit	Line	Data
b20c38a9 SR	1	/*
	2	* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_THEADORABLE_H
	8	#define _CONFIG_THEADORABLE_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_DISPLAY_BOARDINFO_LATE
	14
	15	/*
	16	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	17	* for DDR ECC byte filling in the SPL before loading the main
	18	* U-Boot into it.
	19	*/
	20	#define CONFIG_SYS_TEXT_BASE 0x00800000
	21	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	22
	23	/*
	24	* Commands configuration
	25	*/
	26	#define CONFIG_CMD_BOOTZ
	27	#define CONFIG_CMD_CACHE
	28	#define CONFIG_CMD_ENV
	29	#define CONFIG_CMD_EXT2
	30	#define CONFIG_CMD_EXT4
	31	#define CONFIG_CMD_FAT
	32	#define CONFIG_CMD_FS_GENERIC
	33	#define CONFIG_CMD_I2C
	34	#define CONFIG_CMD_SATA
	35	#define CONFIG_CMD_TIME
	36
	37	/*
	38	* The debugging version enables USB support via defconfig.
	39	* This version should also enable all other non-production
	40	* interfaces / features.
	41	*/
	42	#ifdef CONFIG_USB
	43	#define CONFIG_CMD_DHCP
	44	#define CONFIG_CMD_PCI
	45	#define CONFIG_CMD_PING
	46	#define CONFIG_CMD_SPI
	47	#define CONFIG_CMD_TFTPPUT
	48	#endif
	49
	50	/* I2C */
	51	#define CONFIG_SYS_I2C
	52	#define CONFIG_SYS_I2C_MVTWSI
	53	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
8ac71da9	54	#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
b20c38a9 SR	55	#define CONFIG_SYS_I2C_SLAVE 0x0
	56	#define CONFIG_SYS_I2C_SPEED 100000
	57
	58	/* USB/EHCI configuration */
	59	#define CONFIG_EHCI_IS_TDI
	60	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
	61
	62	#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
	63
	64	/* SPI NOR flash default params, used by sf commands */
	65	#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
	66	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	67
	68	/* Environment in SPI NOR flash */
	69	#define CONFIG_ENV_IS_IN_SPI_FLASH
	70	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	71	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	72	#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
	73	#define CONFIG_ENV_OVERWRITE
	74
	75	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
	76	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	77
	78	#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
	79	#define CONFIG_SYS_ALT_MEMTEST
	80	#define CONFIG_PREBOOT
b20c38a9	81
b20c38a9 SR	82
	83	/* Keep device tree and initrd in lower memory so the kernel can access them */
	84	#define CONFIG_EXTRA_ENV_SETTINGS \
	85	"fdt_high=0x10000000\0" \
	86	"initrd_high=0x10000000\0"
	87
	88	/* SATA support */
	89	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	90	#define CONFIG_SATA_MV
	91	#define CONFIG_LIBATA
	92	#define CONFIG_LBA48
	93	#define CONFIG_EFI_PARTITION
	94	#define CONFIG_DOS_PARTITION
	95
	96	/* Additional FS support/configuration */
	97	#define CONFIG_SUPPORT_VFAT
	98
	99	/* PCIe support */
	100	#ifdef CONFIG_CMD_PCI
	101	#ifndef CONFIG_SPL_BUILD
	102	#define CONFIG_PCI
	103	#define CONFIG_PCI_MVEBU
	104	#define CONFIG_PCI_PNP
169a8550	105	#define CONFIG_BOARD_LATE_INIT /* for PEX switch test */
b20c38a9 SR	106	#endif
	107	#endif
	108
	109	/* Enable LCD and reserve 512KB from top of memory*/
	110	#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
	111
	112	#define CONFIG_VIDEO
	113	#define CONFIG_CFB_CONSOLE
	114	#define CONFIG_VGA_AS_SINGLE_DEVICE
	115	#define CONFIG_CMD_BMP
	116
aea02abe SR	117	/* FPGA programming support */
	118	#define CONFIG_FPGA
	119	#define CONFIG_FPGA_ALTERA
	120	#define CONFIG_FPGA_STRATIX_V
	121
28226b9a SR	122	/*
	123	* Bootcounter
	124	*/
	125	#define CONFIG_BOOTCOUNT_LIMIT
	126	#define CONFIG_BOOTCOUNT_RAM
	127	/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
	128	#define BOOTCOUNT_ADDR 0x1000
	129
b20c38a9 SR	130	/*
	131	* mv-common.h should be defined after CMD configs since it used them
	132	* to enable certain macros
	133	*/
	134	#include "mv-common.h"
	135
	136	/*
	137	* Memory layout while starting into the bin_hdr via the
	138	* BootROM:
	139	*
	140	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	141	* 0x4000.4030 bin_hdr start address
	142	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	143	* 0x4007.fffc BootROM stack top
	144	*
	145	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	146	* L2 cache thus cannot be used.
	147	*/
	148
	149	/* SPL */
	150	/* Defines for SPL */
	151	#define CONFIG_SPL_FRAMEWORK
	152	#define CONFIG_SPL_TEXT_BASE 0x40004030
	153	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	154
	155	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	156	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	157
	158	#ifdef CONFIG_SPL_BUILD
	159	#define CONFIG_SYS_MALLOC_SIMPLE
	160	#endif
	161
	162	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	163	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	164
	165	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	166	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	167	#define CONFIG_SPL_SERIAL_SUPPORT
	168	#define CONFIG_SPL_I2C_SUPPORT
	169
	170	/* SPL related SPI defines */
	171	#define CONFIG_SPL_SPI_SUPPORT
	172	#define CONFIG_SPL_SPI_FLASH_SUPPORT
	173	#define CONFIG_SPL_SPI_LOAD
	174	#define CONFIG_SPL_SPI_BUS 0
	175	#define CONFIG_SPL_SPI_CS 0
	176	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
	177	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
	178
	179	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
	180	#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
	181
	182	#endif /* _CONFIG_THEADORABLE_H */