[people/ms/u-boot.git] / include / configs / theadorable.h

/*
 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_THEADORABLE_H
#define _CONFIG_THEADORABLE_H

/*
 * High Level Configuration Options (easy to change)
 */
#define CONFIG_DISPLAY_BOARDINFO_LATE

/*
 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
 * for DDR ECC byte filling in the SPL before loading the main
 * U-Boot into it.
 */
#define CONFIG_SYS_TCLK		250000000	/* 250MHz */

/*
 * Commands configuration
 */

/*
 * The debugging version enables USB support via defconfig.
 * This version should also enable all other non-production
 * interfaces / features.
 */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
#define CONFIG_I2C_MVTWSI_BASE1		MVEBU_TWSI1_BASE
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000

/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3

/* SPI NOR flash default params, used by sf commands */
#define CONFIG_SF_DEFAULT_SPEED		27777777 /* for fast SPL booting */
#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3

/* Environment in SPI NOR flash */
#define CONFIG_ENV_OFFSET		(1 << 20) /* 1MiB in */
#define CONFIG_ENV_SIZE			(64 << 10) /* 64KiB */
#define CONFIG_ENV_SECT_SIZE		(256 << 10) /* 256KiB sectors */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_PHY_MARVELL		/* there is a marvell phy */
#define PHY_ANEG_TIMEOUT	8000	/* PHY needs a longer aneg time */

#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_PREBOOT

/* Keep device tree and initrd in lower memory so the kernel can access them */
#define CONFIG_EXTRA_ENV_SETTINGS	\
	"fdt_high=0x10000000\0"		\
	"initrd_high=0x10000000\0"

/* SATA support */
#define CONFIG_SYS_SATA_MAX_DEVICE	1
#define CONFIG_LBA48

/* PCIe support */
#ifdef CONFIG_CMD_PCI
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_MVEBU
#endif
#endif

/* Enable LCD and reserve 512KB from top of memory*/
#define CONFIG_SYS_MEM_TOP_HIDE		0x80000

/* FPGA programming support */
#define CONFIG_FPGA_STRATIX_V

/*
 * Bootcounter
 */
#define CONFIG_BOOTCOUNT_RAM
/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
#define BOOTCOUNT_ADDR			0x1000

/*
 * mv-common.h should be defined after CMD configs since it used them
 * to enable certain macros
 */
#include "mv-common.h"

/*
 * Memory layout while starting into the bin_hdr via the
 * BootROM:
 *
 * 0x4000.4000 - 0x4003.4000	headers space (192KiB)
 * 0x4000.4030			bin_hdr start address
 * 0x4003.4000 - 0x4004.7c00	BootROM memory allocations (15KiB)
 * 0x4007.fffc			BootROM stack top
 *
 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
 * L2 cache thus cannot be used.
 */

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x40004030
#define CONFIG_SPL_MAX_SIZE		((128 << 10) - 0x4030)

#define CONFIG_SPL_BSS_START_ADDR	(0x40000000 + (128 << 10))
#define CONFIG_SPL_BSS_MAX_SIZE		(16 << 10)

#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_MALLOC_SIMPLE
#endif

#define CONFIG_SPL_STACK		(0x40000000 + ((192 - 16) << 10))
#define CONFIG_SPL_BOOTROM_SAVE		(CONFIG_SPL_STACK + 4)

/* SPL related SPI defines */
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x1a000
#define CONFIG_SYS_U_BOOT_OFFS		CONFIG_SYS_SPI_U_BOOT_OFFS

/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
#define CONFIG_DDR_FIXED_SIZE		(2 << 20)	/* 2GiB */

#endif /* _CONFIG_THEADORABLE_H */
Commit	Line	Data
b20c38a9 SR	1	/*
	2	* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_THEADORABLE_H
	8	#define _CONFIG_THEADORABLE_H
	9
	10	/*
	11	* High Level Configuration Options (easy to change)
	12	*/
	13	#define CONFIG_DISPLAY_BOARDINFO_LATE
	14
	15	/*
	16	* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
	17	* for DDR ECC byte filling in the SPL before loading the main
	18	* U-Boot into it.
	19	*/
b20c38a9 SR	20	#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
	21
	22	/*
	23	* Commands configuration
	24	*/
b20c38a9 SR	25
	26	/*
	27	* The debugging version enables USB support via defconfig.
	28	* This version should also enable all other non-production
	29	* interfaces / features.
	30	*/
b20c38a9 SR	31
	32	/* I2C */
	33	#define CONFIG_SYS_I2C
	34	#define CONFIG_SYS_I2C_MVTWSI
	35	#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
8ac71da9	36	#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
b20c38a9 SR	37	#define CONFIG_SYS_I2C_SLAVE 0x0
	38	#define CONFIG_SYS_I2C_SPEED 100000
	39
	40	/* USB/EHCI configuration */
	41	#define CONFIG_EHCI_IS_TDI
	42	#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
	43
b20c38a9 SR	44	/* SPI NOR flash default params, used by sf commands */
	45	#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
	46	#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	47
	48	/* Environment in SPI NOR flash */
b20c38a9 SR	49	#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
	50	#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
	51	#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
	52	#define CONFIG_ENV_OVERWRITE
	53
	54	#define CONFIG_PHY_MARVELL /* there is a marvell phy */
	55	#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
	56
b20c38a9 SR	57	#define CONFIG_SYS_ALT_MEMTEST
b20c38a9 SR	58	#define CONFIG_PREBOOT
b20c38a9	59
b20c38a9 SR	60	/* Keep device tree and initrd in lower memory so the kernel can access them */
	61	#define CONFIG_EXTRA_ENV_SETTINGS \
	62	"fdt_high=0x10000000\0" \
	63	"initrd_high=0x10000000\0"
	64
	65	/* SATA support */
	66	#define CONFIG_SYS_SATA_MAX_DEVICE 1
b20c38a9	67	#define CONFIG_LBA48
b20c38a9	68
b20c38a9 SR	69	/* PCIe support */
	70	#ifdef CONFIG_CMD_PCI
	71	#ifndef CONFIG_SPL_BUILD
b20c38a9	72	#define CONFIG_PCI_MVEBU
b20c38a9 SR	73	#endif
	74	#endif
	75
	76	/* Enable LCD and reserve 512KB from top of memory*/
	77	#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
	78
aea02abe	79	/* FPGA programming support */
aea02abe SR	80	#define CONFIG_FPGA_STRATIX_V
aea02abe SR	81
28226b9a SR	82	/*
	83	* Bootcounter
	84	*/
28226b9a SR	85	#define CONFIG_BOOTCOUNT_RAM
	86	/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
	87	#define BOOTCOUNT_ADDR 0x1000
	88
b20c38a9 SR	89	/*
	90	* mv-common.h should be defined after CMD configs since it used them
	91	* to enable certain macros
	92	*/
	93	#include "mv-common.h"
	94
	95	/*
	96	* Memory layout while starting into the bin_hdr via the
	97	* BootROM:
	98	*
	99	* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
	100	* 0x4000.4030 bin_hdr start address
	101	* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
	102	* 0x4007.fffc BootROM stack top
	103	*
	104	* The address space between 0x4007.fffc and 0x400f.fff is not locked in
	105	* L2 cache thus cannot be used.
	106	*/
	107
	108	/* SPL */
	109	/* Defines for SPL */
b20c38a9 SR	110	#define CONFIG_SPL_TEXT_BASE 0x40004030
	111	#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
	112
	113	#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
	114	#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
	115
	116	#ifdef CONFIG_SPL_BUILD
	117	#define CONFIG_SYS_MALLOC_SIMPLE
	118	#endif
	119
	120	#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
	121	#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
	122
b20c38a9	123	/* SPL related SPI defines */
b20c38a9	124	#define CONFIG_SPL_SPI_LOAD
b20c38a9 SR	125	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
	126	#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
	127
	128	/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
	129	#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
	130
	131	#endif /* _CONFIG_THEADORABLE_H */