projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 746f985a ST |
1 | /** |
| 2 | * (C) Copyright 2014, Cavium Inc. | |
| 3 | * | |
| 4 | * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | **/ | |
| 6 | ||
| 7 | #ifndef __THUNDERX_88XX_H__ | |
| 8 | #define __THUNDERX_88XX_H__ | |
| 9 | ||
| 10 | #define CONFIG_REMAKE_ELF | |
| 11 | ||
| 12 | #define CONFIG_THUNDERX | |
| 13 | ||
| 14 | #define CONFIG_SYS_64BIT | |
| 15 | ||
| 746f985a ST |
16 | #define MEM_BASE 0x00500000 |
| 17 | ||
| 900f88f3 ST |
18 | #define CONFIG_SYS_LOWMEM_BASE MEM_BASE |
| 19 | ||
| 746f985a ST |
20 | /* Link Definitions */ |
| 21 | #define CONFIG_SYS_TEXT_BASE 0x00500000 | |
| 22 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) | |
| 23 | ||
| 746f985a ST |
24 | /* SMP Spin Table Definitions */ |
| 25 | #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) | |
| 26 | ||
| 746f985a ST |
27 | /* Generic Timer Definitions */ |
| 28 | #define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ | |
| 29 | ||
| 746f985a ST |
30 | #define CONFIG_SYS_MEMTEST_START MEM_BASE |
| 31 | #define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) | |
| 32 | ||
| 33 | /* Size of malloc() pool */ | |
| 34 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) | |
| 35 | ||
| 36 | /* PL011 Serial Configuration */ | |
| 37 | ||
| 38 | #define CONFIG_PL01X_SERIAL | |
| 39 | #define CONFIG_PL011_CLOCK 24000000 | |
| 40 | #define CONFIG_CONS_INDEX 1 | |
| 41 | ||
| 42 | /* Generic Interrupt Controller Definitions */ | |
| 43 | #define GICD_BASE (0x801000000000) | |
| 44 | #define GICR_BASE (0x801000002000) | |
| 45 | #define CONFIG_SYS_SERIAL0 0x87e024000000 | |
| 46 | #define CONFIG_SYS_SERIAL1 0x87e025000000 | |
| 47 | ||
| 48 | #define CONFIG_BAUDRATE 115200 | |
| 49 | ||
| 746f985a ST |
50 | /* BOOTP options */ |
| 51 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 52 | #define CONFIG_BOOTP_BOOTPATH | |
| 53 | #define CONFIG_BOOTP_GATEWAY | |
| 54 | #define CONFIG_BOOTP_HOSTNAME | |
| 55 | #define CONFIG_BOOTP_PXE | |
| 746f985a ST |
56 | |
| 57 | /* Miscellaneous configurable options */ | |
| 58 | #define CONFIG_SYS_LOAD_ADDR (MEM_BASE) | |
| 59 | ||
| 60 | /* Physical Memory Map */ | |
| 61 | #define CONFIG_NR_DRAM_BANKS 1 | |
| 62 | #define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ | |
| 63 | #define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ | |
| 64 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
| 65 | ||
| 66 | /* Initial environment variables */ | |
| 67 | #define UBOOT_IMG_HEAD_SIZE 0x40 | |
| 68 | /* C80000 - 0x40 */ | |
| 69 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 70 | "kernel_addr=08007ffc0\0" \ | |
| 71 | "fdt_addr=0x94C00000\0" \ | |
| 72 | "fdt_high=0x9fffffff\0" | |
| 73 | ||
| 74 | #define CONFIG_BOOTARGS \ | |
| 75 | "console=ttyAMA0,115200n8 " \ | |
| 76 | "earlycon=pl011,0x87e024000000 " \ | |
| 77 | "debug maxcpus=48 rootwait rw "\ | |
| 78 | "root=/dev/sda2 coherent_pool=16M" | |
| 746f985a ST |
79 | |
| 80 | /* Do not preserve environment */ | |
| 81 | #define CONFIG_ENV_IS_NOWHERE 1 | |
| 82 | #define CONFIG_ENV_SIZE 0x1000 | |
| 83 | ||
| 84 | /* Monitor Command Prompt */ | |
| 85 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
| 86 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 87 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 746f985a ST |
88 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 89 | #define CONFIG_SYS_LONGHELP | |
| 90 | #define CONFIG_CMDLINE_EDITING 1 | |
| 91 | #define CONFIG_SYS_MAXARGS 64 /* max command args */ | |
| 92 | #define CONFIG_NO_RELOCATION 1 | |
| 93 | #define CONFIG_LIB_RAND | |
| 94 | #define PLL_REF_CLK 50000000 /* 50 MHz */ | |
| 95 | #define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) | |
| 96 | ||
| 97 | #endif /* __THUNDERX_88XX_H__ */ |