[people/ms/u-boot.git] / include / configs / ti816x_evm.h

/*
 * ti816x_evm.h
 *
 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
 * Antoine Tenart, <atenart@adeneo-embedded.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H

#define CONFIG_TI81XX
#define CONFIG_TI816X
#define CONFIG_SYS_NO_FLASH
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON

#define CONFIG_ARCH_CPU_INIT

#include <asm/arch/omap.h>

#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (32 * 1024))
#define CONFIG_SYS_LONGHELP		/* undef save memory */
#define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG		/* required for ramdisk support */

#define CONFIG_DISPLAY_CPUINFO

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"loadaddr=0x81000000\0"		\

#define CONFIG_BOOTCOMMAND			\
	"mmc rescan;"				\
	"fatload mmc 0 ${loadaddr} uImage;"	\
	"bootm ${loadaddr}"			\

#define CONFIG_BOOTARGS	"console=ttyO2,115200n8 noinitrd earlyprintk"

/* Clock Defines */
#define V_OSCK          24000000    /* Clock output from T2 */
#define V_SCLK          (V_OSCK >> 1)

#define CONFIG_SYS_MAXARGS	32
#define CONFIG_SYS_CBSIZE	512 /* console I/O buffer size */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* boot arg buffer size */

#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */

#define CONFIG_CMD_ASKEN
#define CONFIG_OMAP_GPIO
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

#define CONFIG_FS_FAT

/*
 * Only one of the following two options (DDR3/DDR2) should be enabled
 * CONFIG_TI816X_EVM_DDR2
 * CONFIG_TI816X_EVM_DDR3
 */
#define CONFIG_TI816X_EVM_DDR3

/*
 * Supported values: 400, 531, 675 or 796 MHz
 */
#define CONFIG_TI816X_DDR_PLL_796

#define CONFIG_TI816X_USE_EMIF0	1
#define CONFIG_TI816X_USE_EMIF1	1

#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 banks of DRAM */
#define PHYS_DRAM_1		0x80000000	/* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE        0x40000000	/* 1 GB */
#define PHYS_DRAM_2		0xC0000000	/* DRAM Bank #2 */
#define PHYS_DRAM_2_SIZE	0x40000000	/* 1 GB */

#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
		GENERATED_GBL_DATA_SIZE)

/**
 * Platform/Board specific defs
 */
#define CONFIG_SYS_CLK_FREQ     27000000
#define CONFIG_SYS_TIMERBASE    0x4802E000
#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */

#undef CONFIG_NAND_OMAP_GPMC

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK      (48000000)
#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */

#define CONFIG_BAUDRATE     115200

/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_SERIAL1
#define CONFIG_SERIAL2
#define CONFIG_SERIAL3
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_CONSOLE_INFO_QUIET

#define CONFIG_ENV_IS_NOWHERE

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE    0x40400000
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR   0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS      0x200 /* 256 KB */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"

#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS  0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE  0x40000
#define CONFIG_SPL_LDSCRIPT     "$(CPUDIR)/omap-common/u-boot-spl.lds"

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_TEXT_BASE        0x80800000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE  0x100000

/* Since SPL did pll and ddr initialization for us,
 * we don't need to do it twice.
 */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/* Unsupported features */
#undef CONFIG_USE_IRQ

#endif
Commit	Line	Data
425faf74 TA	1	/*
	2	* ti816x_evm.h
	3	*
	4	* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
	5	* Antoine Tenart, <atenart@adeneo-embedded.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_TI816X_EVM_H
	11	#define __CONFIG_TI816X_EVM_H
	12
	13	#define CONFIG_TI81XX
	14	#define CONFIG_TI816X
	15	#define CONFIG_SYS_NO_FLASH
	16	#define CONFIG_OMAP
	17	#define CONFIG_OMAP_COMMON
	18
	19	#define CONFIG_ARCH_CPU_INIT
	20
	21	#include <asm/arch/omap.h>
	22
	23	#define CONFIG_ENV_SIZE 0x2000
	24	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
	25	#define CONFIG_SYS_LONGHELP /* undef save memory */
425faf74 TA	26	#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
425faf74 TA	27
425faf74 TA	28	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	29	#define CONFIG_SETUP_MEMORY_TAGS
	30	#define CONFIG_INITRD_TAG /* required for ramdisk support */
	31
425faf74 TA	32	#define CONFIG_DISPLAY_CPUINFO
425faf74 TA	33
425faf74 TA	34	#define CONFIG_EXTRA_ENV_SETTINGS \
	35	"loadaddr=0x81000000\0" \
	36
	37	#define CONFIG_BOOTCOMMAND \
	38	"mmc rescan;" \
	39	"fatload mmc 0 ${loadaddr} uImage;" \
	40	"bootm ${loadaddr}" \
	41
	42	#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
	43
	44	/* Clock Defines */
	45	#define V_OSCK 24000000 /* Clock output from T2 */
	46	#define V_SCLK (V_OSCK >> 1)
	47
	48	#define CONFIG_SYS_MAXARGS 32
	49	#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
	50	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
	51	+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
	52	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
	53
425faf74	54	#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
425faf74 TA	55
425faf74 TA	56	#define CONFIG_CMD_ASKEN
425faf74 TA	57	#define CONFIG_OMAP_GPIO
	58	#define CONFIG_MMC
	59	#define CONFIG_GENERIC_MMC
	60	#define CONFIG_OMAP_HSMMC
425faf74	61	#define CONFIG_DOS_PARTITION
425faf74 TA	62
	63	#define CONFIG_FS_FAT
	64
	65	/*
	66	* Only one of the following two options (DDR3/DDR2) should be enabled
	67	* CONFIG_TI816X_EVM_DDR2
	68	* CONFIG_TI816X_EVM_DDR3
	69	*/
	70	#define CONFIG_TI816X_EVM_DDR3
	71
	72	/*
	73	* Supported values: 400, 531, 675 or 796 MHz
	74	*/
	75	#define CONFIG_TI816X_DDR_PLL_796
	76
	77	#define CONFIG_TI816X_USE_EMIF0 1
	78	#define CONFIG_TI816X_USE_EMIF1 1
	79
425faf74 TA	80	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
	81	#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
	82	#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
	83	#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
	84	#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
	85
	86	#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
	87	#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
	88	#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
	89	GENERATED_GBL_DATA_SIZE)
	90
	91	/**
	92	* Platform/Board specific defs
	93	*/
	94	#define CONFIG_SYS_CLK_FREQ 27000000
	95	#define CONFIG_SYS_TIMERBASE 0x4802E000
	96	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	97
	98	#undef CONFIG_NAND_OMAP_GPMC
	99
	100	/*
	101	* NS16550 Configuration
	102	*/
425faf74 TA	103	#define CONFIG_SYS_NS16550_SERIAL
	104	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	105	#define CONFIG_SYS_NS16550_CLK (48000000)
	106	#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
	107
	108	#define CONFIG_BAUDRATE 115200
	109
	110	/* allow overwriting serial config and ethaddr */
	111	#define CONFIG_ENV_OVERWRITE
	112
	113	#define CONFIG_SERIAL1
	114	#define CONFIG_SERIAL2
	115	#define CONFIG_SERIAL3
	116	#define CONFIG_CONS_INDEX 1
	117	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	118
	119	#define CONFIG_ENV_IS_NOWHERE
	120
	121	/* SPL */
	122	/* Defines for SPL */
425faf74 TA	123	#define CONFIG_SPL_FRAMEWORK
425faf74 TA	124	#define CONFIG_SPL_TEXT_BASE 0x40400000
fa2f81b0 TR	125	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	126	CONFIG_SPL_TEXT_BASE)
425faf74 TA	127
	128	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	129	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	130
	131	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	132	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
e2ccdf89	133	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	134	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
425faf74	135
425faf74	136	#define CONFIG_SPL_SERIAL_SUPPORT
425faf74 TA	137	#define CONFIG_SPL_YMODEM_SUPPORT
	138	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
	139	#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
	140	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	141
	142	#define CONFIG_SPL_BOARD_INIT
	143
	144	#define CONFIG_SYS_TEXT_BASE 0x80800000
	145	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	146	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	147
	148	/* Since SPL did pll and ddr initialization for us,
	149	* we don't need to do it twice.
	150	*/
	151	#ifndef CONFIG_SPL_BUILD
	152	#define CONFIG_SKIP_LOWLEVEL_INIT
	153	#endif
	154
	155	/* Unsupported features */
	156	#undef CONFIG_USE_IRQ
	157
	158	#endif