[people/ms/u-boot.git] / include / configs / ti816x_evm.h

/*
 * ti816x_evm.h
 *
 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
 * Antoine Tenart, <atenart@adeneo-embedded.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_TI816X_EVM_H
#define __CONFIG_TI816X_EVM_H

#define CONFIG_TI81XX
#define CONFIG_TI816X
#define CONFIG_OMAP

#define CONFIG_ARCH_CPU_INIT

#include <asm/arch/omap.h>

#define CONFIG_ENV_SIZE			0x2000
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (32 * 1024))
#define CONFIG_SYS_LONGHELP		/* undef save memory */
#define CONFIG_MACH_TYPE		MACH_TYPE_TI8168EVM

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG		/* required for ramdisk support */

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"loadaddr=0x81000000\0"		\

#define CONFIG_BOOTCOMMAND			\
	"mmc rescan;"				\
	"fatload mmc 0 ${loadaddr} uImage;"	\
	"bootm ${loadaddr}"			\

#define CONFIG_BOOTARGS	"console=ttyO2,115200n8 noinitrd earlyprintk"

/* Clock Defines */
#define V_OSCK          24000000    /* Clock output from T2 */
#define V_SCLK          (V_OSCK >> 1)

#define CONFIG_SYS_MAXARGS	32
#define CONFIG_SYS_CBSIZE	512 /* console I/O buffer size */
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE \
		+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* boot arg buffer size */

#define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */

#define CONFIG_CMD_ASKEN
#define CONFIG_OMAP_GPIO

#define CONFIG_FS_FAT

/*
 * Only one of the following two options (DDR3/DDR2) should be enabled
 * CONFIG_TI816X_EVM_DDR2
 * CONFIG_TI816X_EVM_DDR3
 */
#define CONFIG_TI816X_EVM_DDR3

/*
 * Supported values: 400, 531, 675 or 796 MHz
 */
#define CONFIG_TI816X_DDR_PLL_796

#define CONFIG_TI816X_USE_EMIF0	1
#define CONFIG_TI816X_USE_EMIF1	1

#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 banks of DRAM */
#define PHYS_DRAM_1		0x80000000	/* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE        0x40000000	/* 1 GB */
#define PHYS_DRAM_2		0xC0000000	/* DRAM Bank #2 */
#define PHYS_DRAM_2_SIZE	0x40000000	/* 1 GB */

#define CONFIG_MAX_RAM_BANK_SIZE	(2048 << 20)	/* 2048MB */
#define CONFIG_SYS_SDRAM_BASE		PHYS_DRAM_1
#define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
		GENERATED_GBL_DATA_SIZE)

/**
 * Platform/Board specific defs
 */
#define CONFIG_SYS_CLK_FREQ     27000000
#define CONFIG_SYS_TIMERBASE    0x4802E000
#define CONFIG_SYS_PTV          2   /* Divisor: 2^(PTV+1) => 8 */

#undef CONFIG_NAND_OMAP_GPMC

/*
 * NS16550 Configuration
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK      (48000000)
#define CONFIG_SYS_NS16550_COM1     0x48024000  /* Base EVM has UART2 */

#define CONFIG_BAUDRATE     115200

/* allow overwriting serial config and ethaddr */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_SERIAL1
#define CONFIG_SERIAL2
#define CONFIG_SERIAL3
#define CONFIG_CONS_INDEX	1

#define CONFIG_ENV_IS_NOWHERE

/* SPL */
/* Defines for SPL */
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE    0x40400000
#define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
					 CONFIG_SPL_TEXT_BASE)

#define CONFIG_SPL_BSS_START_ADDR   0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE     0x80000     /* 512 KB */

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME        "u-boot.img"

#define CONFIG_SYS_SPI_U_BOOT_OFFS  0x20000
#define CONFIG_SYS_SPI_U_BOOT_SIZE  0x40000
#define CONFIG_SPL_LDSCRIPT     "arch/arm/mach-omap2/u-boot-spl.lds"

#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SYS_TEXT_BASE        0x80800000
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE  0x100000

/* Since SPL did pll and ddr initialization for us,
 * we don't need to do it twice.
 */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif

/* Unsupported features */
#undef CONFIG_USE_IRQ

#endif
Commit	Line	Data
425faf74 TA	1	/*
	2	* ti816x_evm.h
	3	*
	4	* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
	5	* Antoine Tenart, <atenart@adeneo-embedded.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_TI816X_EVM_H
	11	#define __CONFIG_TI816X_EVM_H
	12
	13	#define CONFIG_TI81XX
	14	#define CONFIG_TI816X
425faf74	15	#define CONFIG_OMAP
425faf74 TA	16
	17	#define CONFIG_ARCH_CPU_INIT
	18
	19	#include <asm/arch/omap.h>
	20
	21	#define CONFIG_ENV_SIZE 0x2000
	22	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
	23	#define CONFIG_SYS_LONGHELP /* undef save memory */
425faf74 TA	24	#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
425faf74 TA	25
425faf74 TA	26	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	27	#define CONFIG_SETUP_MEMORY_TAGS
	28	#define CONFIG_INITRD_TAG /* required for ramdisk support */
	29
425faf74 TA	30	#define CONFIG_EXTRA_ENV_SETTINGS \
	31	"loadaddr=0x81000000\0" \
	32
	33	#define CONFIG_BOOTCOMMAND \
	34	"mmc rescan;" \
	35	"fatload mmc 0 ${loadaddr} uImage;" \
	36	"bootm ${loadaddr}" \
	37
	38	#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
	39
	40	/* Clock Defines */
	41	#define V_OSCK 24000000 /* Clock output from T2 */
	42	#define V_SCLK (V_OSCK >> 1)
	43
	44	#define CONFIG_SYS_MAXARGS 32
	45	#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
	46	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
	47	+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
	48	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
	49
425faf74	50	#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
425faf74 TA	51
425faf74 TA	52	#define CONFIG_CMD_ASKEN
425faf74	53	#define CONFIG_OMAP_GPIO
425faf74 TA	54
	55	#define CONFIG_FS_FAT
	56
	57	/*
	58	* Only one of the following two options (DDR3/DDR2) should be enabled
	59	* CONFIG_TI816X_EVM_DDR2
	60	* CONFIG_TI816X_EVM_DDR3
	61	*/
	62	#define CONFIG_TI816X_EVM_DDR3
	63
	64	/*
	65	* Supported values: 400, 531, 675 or 796 MHz
	66	*/
	67	#define CONFIG_TI816X_DDR_PLL_796
	68
	69	#define CONFIG_TI816X_USE_EMIF0 1
	70	#define CONFIG_TI816X_USE_EMIF1 1
	71
425faf74 TA	72	#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
	73	#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
	74	#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
	75	#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
	76	#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
	77
	78	#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
	79	#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
	80	#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
	81	GENERATED_GBL_DATA_SIZE)
	82
	83	/**
	84	* Platform/Board specific defs
	85	*/
	86	#define CONFIG_SYS_CLK_FREQ 27000000
	87	#define CONFIG_SYS_TIMERBASE 0x4802E000
	88	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	89
	90	#undef CONFIG_NAND_OMAP_GPMC
	91
	92	/*
	93	* NS16550 Configuration
	94	*/
425faf74 TA	95	#define CONFIG_SYS_NS16550_SERIAL
	96	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	97	#define CONFIG_SYS_NS16550_CLK (48000000)
	98	#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
	99
	100	#define CONFIG_BAUDRATE 115200
	101
	102	/* allow overwriting serial config and ethaddr */
	103	#define CONFIG_ENV_OVERWRITE
	104
	105	#define CONFIG_SERIAL1
	106	#define CONFIG_SERIAL2
	107	#define CONFIG_SERIAL3
	108	#define CONFIG_CONS_INDEX 1
425faf74 TA	109
	110	#define CONFIG_ENV_IS_NOWHERE
	111
	112	/* SPL */
	113	/* Defines for SPL */
425faf74 TA	114	#define CONFIG_SPL_FRAMEWORK
425faf74 TA	115	#define CONFIG_SPL_TEXT_BASE 0x40400000
fa2f81b0 TR	116	#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
fa2f81b0 TR	117	CONFIG_SPL_TEXT_BASE)
425faf74 TA	118
	119	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	120	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	121
e2ccdf89	122	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
205b4f33	123	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
425faf74	124
425faf74 TA	125	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
425faf74 TA	126	#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
983e3700	127	#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
425faf74 TA	128
	129	#define CONFIG_SPL_BOARD_INIT
	130
	131	#define CONFIG_SYS_TEXT_BASE 0x80800000
	132	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	133	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	134
	135	/* Since SPL did pll and ddr initialization for us,
	136	* we don't need to do it twice.
	137	*/
	138	#ifndef CONFIG_SPL_BUILD
	139	#define CONFIG_SKIP_LOWLEVEL_INIT
	140	#endif
	141
	142	/* Unsupported features */
	143	#undef CONFIG_USE_IRQ
	144
	145	#endif