[people/ms/u-boot.git] / include / configs / ti_armv7_keystone2.h

/*
 * Common configuration header file for all Keystone II EVM platforms
 *
 * (C) Copyright 2012-2014
 *     Texas Instruments Incorporated, <www.ti.com>
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#ifndef __CONFIG_KS2_EVM_H
#define __CONFIG_KS2_EVM_H

#define CONFIG_SOC_KEYSTONE

/* U-Boot Build Configuration */
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 2nd stage loader */

/* SoC Configuration */
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_ARCH_TIMER
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE		0x0c000000
#endif
#define CONFIG_SPL_TARGET		"u-boot-spi.gph"
#define CONFIG_SYS_DCACHE_OFF

/* Memory Configuration */
#define CONFIG_NR_DRAM_BANKS		2
#define CONFIG_SYS_LPAE_SDRAM_BASE	0x800000000
#define CONFIG_MAX_RAM_BANK_SIZE	(2 << 30)       /* 2GB */
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SPL_TEXT_BASE - \
					GENERATED_GBL_DATA_SIZE)

#ifdef CONFIG_SYS_MALLOC_F_LEN
#define SPL_MALLOC_F_SIZE	CONFIG_SYS_MALLOC_F_LEN
#else
#define SPL_MALLOC_F_SIZE	0
#endif

/* SPL SPI Loader Configuration */
#define CONFIG_SPL_PAD_TO		65536
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SPL_PAD_TO - 8)
#define CONFIG_SPL_BSS_START_ADDR	(CONFIG_SPL_TEXT_BASE + \
					CONFIG_SPL_MAX_SIZE)
#define CONFIG_SPL_BSS_MAX_SIZE		(32 * 1024)
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
					CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE	(32 * 1024)
#define KEYSTONE_SPL_STACK_SIZE		(8 * 1024)
#define CONFIG_SPL_STACK		(CONFIG_SYS_SPL_MALLOC_START + \
					CONFIG_SYS_SPL_MALLOC_SIZE + \
					SPL_MALLOC_F_SIZE + \
					KEYSTONE_SPL_STACK_SIZE - 4)
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SYS_SPI_U_BOOT_OFFS	CONFIG_SPL_PAD_TO

/* SRAM scratch space entries  */
#define SRAM_SCRATCH_SPACE_ADDR	CONFIG_SPL_STACK + 0x8

#define TI_SRAM_SCRATCH_BOARD_EEPROM_START	(SRAM_SCRATCH_SPACE_ADDR)
#define TI_SRAM_SCRATCH_BOARD_EEPROM_END	(SRAM_SCRATCH_SPACE_ADDR + 0x200)
#define KEYSTONE_SRAM_SCRATCH_SPACE_END		(TI_SRAM_SCRATCH_BOARD_EEPROM_END)

/* UART Configuration */
#define CONFIG_SYS_NS16550_MEM32
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL)
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#endif
#define CONFIG_SYS_NS16550_COM1		KS2_UART0_BASE
#define CONFIG_SYS_NS16550_COM2		KS2_UART1_BASE
#define CONFIG_CONS_INDEX		1

#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_NS16550_CLK		ks_clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_NS16550_CLK		ks_clk_get_rate(uart_pll_clk) / 2
#endif

/* SPI Configuration */
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_CLK		ks_clk_get_rate(KS2_CLK1_6)
#define CONFIG_SF_DEFAULT_SPEED		30000000
#define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#define CONFIG_SYS_SPI0
#define CONFIG_SYS_SPI_BASE		KS2_SPI0_BASE
#define CONFIG_SYS_SPI0_NUM_CS		4
#define CONFIG_SYS_SPI1
#define CONFIG_SYS_SPI1_BASE		KS2_SPI1_BASE
#define CONFIG_SYS_SPI1_NUM_CS		4
#define CONFIG_SYS_SPI2
#define CONFIG_SYS_SPI2_BASE		KS2_SPI2_BASE
#define CONFIG_SYS_SPI2_NUM_CS		4
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
#endif

/* Network Configuration */
#define CONFIG_PHYLIB
#define CONFIG_PHY_MARVELL
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT		32
#define CONFIG_SYS_SGMII_REFCLK_MHZ	312
#define CONFIG_SYS_SGMII_LINERATE_MHZ	1250
#define CONFIG_SYS_SGMII_RATESCALE	2

/* Keyston Navigator Configuration */
#define CONFIG_TI_KSNAV
#define CONFIG_KSNAV_QM_BASE_ADDRESS		KS2_QM_BASE_ADDRESS
#define CONFIG_KSNAV_QM_CONF_BASE		KS2_QM_CONF_BASE
#define CONFIG_KSNAV_QM_DESC_SETUP_BASE		KS2_QM_DESC_SETUP_BASE
#define CONFIG_KSNAV_QM_STATUS_RAM_BASE		KS2_QM_STATUS_RAM_BASE
#define CONFIG_KSNAV_QM_INTD_CONF_BASE		KS2_QM_INTD_CONF_BASE
#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE		KS2_QM_PDSP1_CMD_BASE
#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE		KS2_QM_PDSP1_CTRL_BASE
#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE		KS2_QM_PDSP1_IRAM_BASE
#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE	KS2_QM_MANAGER_QUEUES_BASE
#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE	KS2_QM_MANAGER_Q_PROXY_BASE
#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE	KS2_QM_QUEUE_STATUS_BASE
#define CONFIG_KSNAV_QM_LINK_RAM_BASE		KS2_QM_LINK_RAM_BASE
#define CONFIG_KSNAV_QM_REGION_NUM		KS2_QM_REGION_NUM
#define CONFIG_KSNAV_QM_QPOOL_NUM		KS2_QM_QPOOL_NUM

/* NETCP pktdma */
#define CONFIG_KSNAV_PKTDMA_NETCP
#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE	KS2_NETCP_PDMA_CTRL_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE		KS2_NETCP_PDMA_TX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM	KS2_NETCP_PDMA_TX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE		KS2_NETCP_PDMA_RX_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM	KS2_NETCP_PDMA_RX_CH_NUM
#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE	KS2_NETCP_PDMA_SCHED_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE	KS2_NETCP_PDMA_RX_FLOW_BASE
#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM	KS2_NETCP_PDMA_RX_FLOW_NUM
#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE	KS2_NETCP_PDMA_RX_FREE_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE	KS2_NETCP_PDMA_RX_RCV_QUEUE
#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE	KS2_NETCP_PDMA_TX_SND_QUEUE

/* Keystone net */
#define CONFIG_DRIVER_TI_KEYSTONE_NET
#define CONFIG_KSNET_MAC_ID_BASE		KS2_MAC_ID_BASE_ADDR
#define CONFIG_KSNET_NETCP_BASE			KS2_NETCP_BASE
#define CONFIG_KSNET_SERDES_SGMII_BASE		KS2_SGMII_SERDES_BASE
#define CONFIG_KSNET_SERDES_SGMII2_BASE		KS2_SGMII_SERDES2_BASE
#define CONFIG_KSNET_SERDES_LANES_PER_SGMII	KS2_LANES_PER_SGMII_SERDES

/* SerDes */
#define CONFIG_TI_KEYSTONE_SERDES

#define CONFIG_AEMIF_CNTRL_BASE		KS2_AEMIF_CNTRL_BASE

/* I2C Configuration */
#define CONFIG_SYS_I2C_DAVINCI
#define CONFIG_SYS_DAVINCI_I2C_SPEED	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE	0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED1	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE1	0x10 /* SMBus host address */
#define CONFIG_SYS_DAVINCI_I2C_SPEED2	100000
#define CONFIG_SYS_DAVINCI_I2C_SLAVE2	0x10 /* SMBus host address */
#define I2C_BUS_MAX			3

/* EEPROM definitions */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
#define CONFIG_ENV_EEPROM_IS_ON_I2C

/* NAND Configuration */
#define CONFIG_NAND_DAVINCI
#define CONFIG_KEYSTONE_RBL_NAND
#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE	CONFIG_ENV_OFFSET
#define CONFIG_SYS_NAND_MASK_CLE		0x4000
#define CONFIG_SYS_NAND_MASK_ALE		0x2000
#define CONFIG_SYS_NAND_CS			2
#define CONFIG_SYS_NAND_USE_FLASH_BBT
#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST

#define CONFIG_SYS_NAND_LARGEPAGE
#define CONFIG_SYS_NAND_BASE_LIST		{ 0x30000000, }
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_MAX_CHIPS		1
#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define CONFIG_ENV_SIZE				(256 << 10)  /* 256 KiB */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET			0x100000
#define CONFIG_MTD_PARTITIONS
#define CONFIG_RBTREE
#define CONFIG_LZO
#define MTDIDS_DEFAULT			"nand0=davinci_nand.0"
#define MTDPARTS_DEFAULT		"mtdparts=davinci_nand.0:" \
					"1024k(bootloader)ro,512k(params)ro," \
					"-(ubifs)"

/* USB Configuration */
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS	2
#define CONFIG_FS_FAT
#define CONFIG_USB_SS_BASE			KS2_USB_SS_BASE
#define CONFIG_USB_HOST_XHCI_BASE		KS2_USB_HOST_XHCI_BASE
#define CONFIG_DEV_USB_PHY_BASE			KS2_DEV_USB_PHY_BASE
#define CONFIG_USB_PHY_CFG_BASE			KS2_USB_PHY_CFG_BASE

/* U-Boot command configuration */
#define CONFIG_CMD_SAVES
#define CONFIG_CMD_UBIFS

/* U-Boot general configuration */
#define CONFIG_MISC_INIT_R
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
#define CONFIG_TIMESTAMP

/* EDMA3 */
#define CONFIG_TI_EDMA3

#define KERNEL_MTD_PARTS						\
	"mtdparts="							\
	SPI_MTD_PARTS

#define DEFAULT_FW_INITRAMFS_BOOT_ENV					\
	"name_fw_rd=k2-fw-initrd.cpio.gz\0"				\
	"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0"		\
	"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; "	\
		"run set_rd_spec\0"					\
	"init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; "	\
		"run set_rd_spec\0"					\
	"init_fw_rd_ramfs=setenv rd_spec -\0"				\
	"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; "	\
		"run set_rd_spec\0"					\

#define DEFAULT_PMMC_BOOT_ENV						\
	"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
	"dev_pmmc=0\0"							\
	"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0"	\
	"get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0"	\
	"get_pmmc_ramfs=run get_pmmc_net\0"				\
	"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} "		\
			"${bootdir}/${name_pmmc}\0"			\
	"get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0"	\
	"run_pmmc=rproc init; rproc list; "				\
		"rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; "	\
		"rproc start ${dev_pmmc}\0"				\

#define CONFIG_EXTRA_ENV_SETTINGS					\
	DEFAULT_LINUX_BOOT_ENV						\
	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS				\
	"bootdir=/boot\0" \
	"tftp_root=/\0"							\
	"nfs_root=/export\0"						\
	"mem_lpae=1\0"							\
	"addr_ubi=0x82000000\0"						\
	"addr_secdb_key=0xc000000\0"					\
	"name_kern=zImage\0"						\
	"addr_mon=0x87000000\0"						\
	"run_mon=mon_install ${addr_mon}\0"				\
	"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0"		\
	"init_net=run args_all args_net\0"				\
	"init_nfs=setenv autoload no; dhcp; run args_all args_net\0"	\
	"init_ubi=run args_all args_ubi; "				\
		"ubi part ubifs; ubifsmount ubi:rootfs;\0"			\
	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
	"get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0"	\
	"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0"		\
	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
	"get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0"	\
	"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0"		\
	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
	"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0"	\
	"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0"		\
	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0"	\
	"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
	"burn_uboot_spi=sf probe; sf erase 0 0x80000; "		\
		"sf write ${loadaddr} 0 ${filesize}\0"		\
	"burn_uboot_nand=nand erase 0 0x100000; "			\
		"nand write ${loadaddr} 0 ${filesize}\0"		\
	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 "	\
		KERNEL_MTD_PARTS					\
	"args_net=setenv bootargs ${bootargs} rootfstype=nfs "		\
		"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root},"	\
		"${nfs_options} ip=dhcp\0"				\
	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0"			\
	"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0"	\
	"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0"	\
	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0"	\
	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0"	\
	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0"	\
	"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0"	\
	"burn_ubi=nand erase.part ubifs; "				\
		"nand write ${addr_ubi} ubifs ${filesize}\0"		\
	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0"		\
	"args_ramfs=setenv bootargs ${bootargs} "			\
		"rdinit=/sbin/init rw root=/dev/ram0 "			\
		"initrd=0x808080000,80M\0"				\
	"no_post=1\0"							\
	"mtdparts=mtdparts=davinci_nand.0:"				\
		"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"

#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND						\
	"run init_${boot} get_mon_${boot} run_mon init_fw_rd_${boot} "	\
	"get_fdt_${boot} get_kern_${boot} run_kern"
#endif

#define CONFIG_BOOTARGS							\

/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>

/* we may include files below only after all above definitions */
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#ifndef CONFIG_SOC_K2G
#define CONFIG_SYS_HZ_CLOCK		ks_clk_get_rate(KS2_CLK1_6)
#else
#define CONFIG_SYS_HZ_CLOCK		get_external_clk(sys_clk)
#endif

#endif /* __CONFIG_KS2_EVM_H */
Commit	Line	Data
2221cd12 HZ	1	/*
	2	* Common configuration header file for all Keystone II EVM platforms
	3	*
	4	* (C) Copyright 2012-2014
	5	* Texas Instruments Incorporated, <www.ti.com>
	6	*
	7	* SPDX-License-Identifier: GPL-2.0+
	8	*/
	9
	10	#ifndef __CONFIG_KS2_EVM_H
	11	#define __CONFIG_KS2_EVM_H
	12
	13	#define CONFIG_SOC_KEYSTONE
	14
	15	/* U-Boot Build Configuration */
	16	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */
2221cd12 HZ	17
2221cd12 HZ	18	/* SoC Configuration */
2221cd12 HZ	19	#define CONFIG_ARCH_CPU_INIT
2221cd12 HZ	20	#define CONFIG_SYS_ARCH_TIMER
27ce6965	21	#ifndef CONFIG_SYS_TEXT_BASE
401f2d91	22	#define CONFIG_SYS_TEXT_BASE 0x0c000000
27ce6965	23	#endif
2221cd12 HZ	24	#define CONFIG_SPL_TARGET "u-boot-spi.gph"
	25	#define CONFIG_SYS_DCACHE_OFF
	26
	27	/* Memory Configuration */
	28	#define CONFIG_NR_DRAM_BANKS 2
2221cd12 HZ	29	#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000
2221cd12 HZ	30	#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */
401f2d91	31	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE - \
2221cd12 HZ	32	GENERATED_GBL_DATA_SIZE)
2221cd12 HZ	33
aaf461f9 LV	34	#ifdef CONFIG_SYS_MALLOC_F_LEN
	35	#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN
	36	#else
	37	#define SPL_MALLOC_F_SIZE 0
	38	#endif
	39
2221cd12 HZ	40	/* SPL SPI Loader Configuration */
	41	#define CONFIG_SPL_PAD_TO 65536
	42	#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8)
	43	#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \
	44	CONFIG_SPL_MAX_SIZE)
	45	#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024)
	46	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
	47	CONFIG_SPL_BSS_MAX_SIZE)
	48	#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024)
8ccdba8b	49	#define KEYSTONE_SPL_STACK_SIZE (8 * 1024)
2221cd12 HZ	50	#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \
2221cd12 HZ	51	CONFIG_SYS_SPL_MALLOC_SIZE + \
aaf461f9	52	SPL_MALLOC_F_SIZE + \
8ccdba8b	53	KEYSTONE_SPL_STACK_SIZE - 4)
2221cd12	54	#define CONFIG_SPL_SPI_LOAD
2221cd12	55	#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO
2221cd12	56
a4562d06 FCJ	57	/* SRAM scratch space entries */
	58	#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8
	59
	60	#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR)
	61	#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
	62	#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
	63
2221cd12	64	/* UART Configuration */
2221cd12	65	#define CONFIG_SYS_NS16550_MEM32
391839fb LV	66	#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_DM_SERIAL)
391839fb LV	67	#define CONFIG_SYS_NS16550_SERIAL
2221cd12	68	#define CONFIG_SYS_NS16550_REG_SIZE -4
391839fb	69	#endif
2221cd12 HZ	70	#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
2221cd12 HZ	71	#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
2221cd12	72	#define CONFIG_CONS_INDEX 1
2221cd12	73
e6d71e1c	74	#ifndef CONFIG_SOC_K2G
43ebbfc3	75	#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6)
e6d71e1c	76	#else
43ebbfc3	77	#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2
e6d71e1c VA	78	#endif
e6d71e1c VA	79
2221cd12	80	/* SPI Configuration */
2221cd12	81	#define CONFIG_DAVINCI_SPI
43ebbfc3	82	#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6)
2221cd12 HZ	83	#define CONFIG_SF_DEFAULT_SPEED 30000000
	84	#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	85	#define CONFIG_SYS_SPI0
	86	#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE
	87	#define CONFIG_SYS_SPI0_NUM_CS 4
	88	#define CONFIG_SYS_SPI1
	89	#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE
	90	#define CONFIG_SYS_SPI1_NUM_CS 4
	91	#define CONFIG_SYS_SPI2
	92	#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE
	93	#define CONFIG_SYS_SPI2_NUM_CS 4
39832244 V	94	#ifdef CONFIG_SPL_BUILD
	95	#undef CONFIG_DM_SPI
	96	#undef CONFIG_DM_SPI_FLASH
	97	#endif
2221cd12 HZ	98
2221cd12 HZ	99	/* Network Configuration */
3fe93623 KI	100	#define CONFIG_PHYLIB
3fe93623 KI	101	#define CONFIG_PHY_MARVELL
2221cd12 HZ	102	#define CONFIG_MII
	103	#define CONFIG_BOOTP_DEFAULT
	104	#define CONFIG_BOOTP_DNS
	105	#define CONFIG_BOOTP_DNS2
	106	#define CONFIG_BOOTP_SEND_HOSTNAME
	107	#define CONFIG_NET_RETRY_COUNT 32
2221cd12 HZ	108	#define CONFIG_SYS_SGMII_REFCLK_MHZ 312
	109	#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250
	110	#define CONFIG_SYS_SGMII_RATESCALE 2
	111
ef454717	112	/* Keyston Navigator Configuration */
796bcee6	113	#define CONFIG_TI_KSNAV
ef454717 KI	114	#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS
	115	#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE
	116	#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE
	117	#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE
	118	#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE
	119	#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE
	120	#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE
	121	#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE
	122	#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE
	123	#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE
	124	#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE
	125	#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE
	126	#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM
	127	#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM
	128
	129	/* NETCP pktdma */
796bcee6	130	#define CONFIG_KSNAV_PKTDMA_NETCP
ef454717 KI	131	#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE
	132	#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE
	133	#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM
	134	#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE
	135	#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM
	136	#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE
	137	#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE
	138	#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM
	139	#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE
	140	#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE
	141	#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE
	142
0935cac6	143	/* Keystone net */
796bcee6	144	#define CONFIG_DRIVER_TI_KEYSTONE_NET
92a16c81 HZ	145	#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR
	146	#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE
	147	#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE
3c61502a	148	#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
92a16c81	149	#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
0935cac6	150
87ac27bd KI	151	/* SerDes */
	152	#define CONFIG_TI_KEYSTONE_SERDES
	153
2221cd12 HZ	154	#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
	155
	156	/* I2C Configuration */
2221cd12 HZ	157	#define CONFIG_SYS_I2C_DAVINCI
	158	#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
	159	#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
	160	#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
	161	#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
	162	#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
	163	#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
	164	#define I2C_BUS_MAX 3
	165
	166	/* EEPROM definitions */
2221cd12 HZ	167	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	168	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	169	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	170	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
	171	#define CONFIG_ENV_EEPROM_IS_ON_I2C
	172
	173	/* NAND Configuration */
	174	#define CONFIG_NAND_DAVINCI
	175	#define CONFIG_KEYSTONE_RBL_NAND
	176	#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET
	177	#define CONFIG_SYS_NAND_MASK_CLE 0x4000
	178	#define CONFIG_SYS_NAND_MASK_ALE 0x2000
	179	#define CONFIG_SYS_NAND_CS 2
	180	#define CONFIG_SYS_NAND_USE_FLASH_BBT
	181	#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	182
	183	#define CONFIG_SYS_NAND_LARGEPAGE
	184	#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
	185	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	186	#define CONFIG_SYS_NAND_MAX_CHIPS 1
	187	#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
	188	#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */
	189	#define CONFIG_ENV_IS_IN_NAND
	190	#define CONFIG_ENV_OFFSET 0x100000
	191	#define CONFIG_MTD_PARTITIONS
2221cd12 HZ	192	#define CONFIG_RBTREE
	193	#define CONFIG_LZO
	194	#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
	195	#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \
	196	"1024k(bootloader)ro,512k(params)ro," \
	197	"-(ubifs)"
	198
bc0e8d7c	199	/* USB Configuration */
bc0e8d7c WK	200	#define CONFIG_USB_XHCI_KEYSTONE
bc0e8d7c WK	201	#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
bc0e8d7c	202	#define CONFIG_FS_FAT
bc0e8d7c WK	203	#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE
	204	#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE
	205	#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE
	206	#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE
	207
2221cd12	208	/* U-Boot command configuration */
2221cd12	209	#define CONFIG_CMD_SAVES
2221cd12	210	#define CONFIG_CMD_UBIFS
2221cd12 HZ	211
2221cd12 HZ	212	/* U-Boot general configuration */
8347210a	213	#define CONFIG_MISC_INIT_R
2221cd12 HZ	214	#define CONFIG_CRC32_VERIFY
2221cd12 HZ	215	#define CONFIG_MX_CYCLIC
2221cd12 HZ	216	#define CONFIG_TIMESTAMP
	217
	218	/* EDMA3 */
	219	#define CONFIG_TI_EDMA3
	220
3f18ff07 V	221	#define KERNEL_MTD_PARTS \
	222	"mtdparts=" \
	223	SPI_MTD_PARTS
	224
abca9477 MK	225	#define DEFAULT_FW_INITRAMFS_BOOT_ENV \
	226	"name_fw_rd=k2-fw-initrd.cpio.gz\0" \
	227	"set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \
	228	"init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \
	229	"run set_rd_spec\0" \
979a1f8b AD	230	"init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \
979a1f8b AD	231	"run set_rd_spec\0" \
abca9477 MK	232	"init_fw_rd_ramfs=setenv rd_spec -\0" \
	233	"init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \
	234	"run set_rd_spec\0" \
	235
6f6e9439 NM	236	#define DEFAULT_PMMC_BOOT_ENV \
	237	"set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \
	238	"dev_pmmc=0\0" \
	239	"get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \
979a1f8b	240	"get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \
6f6e9439 NM	241	"get_pmmc_ramfs=run get_pmmc_net\0" \
	242	"get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \
	243	"${bootdir}/${name_pmmc}\0" \
	244	"get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \
	245	"run_pmmc=rproc init; rproc list; " \
	246	"rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \
	247	"rproc start ${dev_pmmc}\0" \
	248
2221cd12	249	#define CONFIG_EXTRA_ENV_SETTINGS \
fd72d318	250	DEFAULT_LINUX_BOOT_ENV \
349c26dd	251	CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \
48dc1657	252	"bootdir=/boot\0" \
2221cd12 HZ	253	"tftp_root=/\0" \
	254	"nfs_root=/export\0" \
	255	"mem_lpae=1\0" \
2221cd12 HZ	256	"addr_ubi=0x82000000\0" \
2221cd12 HZ	257	"addr_secdb_key=0xc000000\0" \
bad773f4	258	"name_kern=zImage\0" \
ceee15ce	259	"addr_mon=0x87000000\0" \
2221cd12	260	"run_mon=mon_install ${addr_mon}\0" \
abca9477	261	"run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \
2221cd12	262	"init_net=run args_all args_net\0" \
c29a3ce4	263	"init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \
2221cd12	264	"init_ubi=run args_all args_ubi; " \
8462cb57	265	"ubi part ubifs; ubifsmount ubi:rootfs;\0" \
fd72d318	266	"get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
c29a3ce4	267	"get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \
48dc1657	268	"get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \
fd72d318	269	"get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
c29a3ce4	270	"get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \
48dc1657	271	"get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \
2221cd12	272	"get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
c29a3ce4	273	"get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \
48dc1657	274	"get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \
8889e984	275	"get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \
c29a3ce4	276	"get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \
7ec2328d	277	"burn_uboot_spi=sf probe; sf erase 0 0x80000; " \
8889e984	278	"sf write ${loadaddr} 0 ${filesize}\0" \
2221cd12	279	"burn_uboot_nand=nand erase 0 0x100000; " \
8889e984	280	"nand write ${loadaddr} 0 ${filesize}\0" \
3f18ff07 V	281	"args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \
3f18ff07 V	282	KERNEL_MTD_PARTS \
2221cd12 HZ	283	"args_net=setenv bootargs ${bootargs} rootfstype=nfs " \
	284	"root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \
	285	"${nfs_options} ip=dhcp\0" \
	286	"nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \
fd72d318 NM	287	"get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \
fd72d318 NM	288	"get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \
2221cd12	289	"get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \
fd72d318	290	"get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \
2221cd12	291	"get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \
c29a3ce4	292	"get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \
2221cd12 HZ	293	"burn_ubi=nand erase.part ubifs; " \
	294	"nand write ${addr_ubi} ubifs ${filesize}\0" \
	295	"init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \
	296	"args_ramfs=setenv bootargs ${bootargs} " \
	297	"rdinit=/sbin/init rw root=/dev/ram0 " \
f06b454b	298	"initrd=0x808080000,80M\0" \
2221cd12 HZ	299	"no_post=1\0" \
	300	"mtdparts=mtdparts=davinci_nand.0:" \
	301	"1024k(bootloader)ro,512k(params)ro,-(ubifs)\0"
	302
6f6e9439	303	#ifndef CONFIG_BOOTCOMMAND
2221cd12	304	#define CONFIG_BOOTCOMMAND \
ceee15ce LV	305	"run init_${boot} get_mon_${boot} run_mon init_fw_rd_${boot} " \
ceee15ce LV	306	"get_fdt_${boot} get_kern_${boot} run_kern"
6f6e9439	307	#endif
2221cd12 HZ	308
	309	#define CONFIG_BOOTARGS \
	310
e07cff11 NM	311	/* Now for the remaining common defines */
	312	#include <configs/ti_armv7_common.h>
	313
2221cd12 HZ	314	/* we may include files below only after all above definitions */
	315	#include <asm/arch/hardware.h>
	316	#include <asm/arch/clock.h>
e6d71e1c	317	#ifndef CONFIG_SOC_K2G
43ebbfc3	318	#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6)
e6d71e1c	319	#else
ee3c6532	320	#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk)
e6d71e1c	321	#endif
2221cd12	322
2221cd12	323	#endif /* __CONFIG_KS2_EVM_H */