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1 | /* |
2 | * ti_armv7_omap.h | |
3 | * | |
4 | * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | * | |
8 | * The various ARMv7 SoCs from TI all share a number of IP blocks when | |
9 | * implementing a given feature. This is meant to isolate the features | |
10 | * that are based on OMAP architecture. | |
11 | */ | |
12 | #ifndef __CONFIG_TI_ARMV7_OMAP_H__ | |
13 | #define __CONFIG_TI_ARMV7_OMAP_H__ | |
14 | ||
15 | /* Common defines for all OMAP architecture based SoCs */ | |
16 | #define CONFIG_OMAP | |
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17 | |
18 | /* I2C IP block */ | |
19 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
20 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
21 | #define CONFIG_SYS_I2C_OMAP24XX | |
22 | ||
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23 | /* SPI IP Block */ |
24 | #define CONFIG_OMAP3_SPI | |
25 | ||
26 | /* GPIO block */ | |
27 | #define CONFIG_OMAP_GPIO | |
28 | ||
29 | /* | |
30 | * GPMC NAND block. We support 1 device and the physical address to | |
31 | * access CS0 at is 0x8000000. | |
32 | */ | |
33 | #ifdef CONFIG_NAND | |
34 | #define CONFIG_NAND_OMAP_GPMC | |
35 | #ifndef CONFIG_SYS_NAND_BASE | |
36 | #define CONFIG_SYS_NAND_BASE 0x8000000 | |
37 | #endif | |
38 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
39 | #define CONFIG_CMD_NAND | |
40 | #endif | |
41 | ||
42 | /* Now for the remaining common defines */ | |
43 | #include <configs/ti_armv7_common.h> | |
44 | ||
45 | #endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ |