projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c7964f86 EBS |
1 | /* |
| 2 | * ti_omap3_common.h | |
| 3 | * | |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | |
| 7 | * | |
| 8 | * For more details, please see the technical documents listed at | |
| 9 | * http://www.ti.com/product/omap3530 | |
| 10 | * http://www.ti.com/product/omap3630 | |
| 11 | * http://www.ti.com/product/dm3730 | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __CONFIG_TI_OMAP3_COMMON_H__ | |
| 15 | #define __CONFIG_TI_OMAP3_COMMON_H__ | |
| 16 | ||
| 3709844f AA |
17 | /* |
| 18 | * High Level Configuration Options | |
| 19 | */ | |
| 20 | ||
| c7964f86 | 21 | #include <asm/arch/cpu.h> |
| 987ec585 | 22 | #include <asm/arch/omap.h> |
| c7964f86 | 23 | |
| c7964f86 EBS |
24 | /* Clock Defines */ |
| 25 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
| 26 | #define V_SCLK (V_OSCK >> 1) | |
| 27 | ||
| 28 | /* NS16550 Configuration */ | |
| 29 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
| c7b9686d | 30 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| 313ed5d5 DW |
31 | #if defined(CONFIG_SPL_BUILD) |
| 32 | #define CONFIG_SYS_NS16550_SERIAL | |
| 33 | #if !defined(CONFIG_DM_SERIAL) | |
| 34 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
| 35 | #endif /* !CONFIG_DM_SERIAL */ | |
| 36 | #endif /* CONFIG_SPL_BUILD */ | |
| c7964f86 EBS |
37 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ |
| 38 | 115200} | |
| 39 | ||
| 40 | /* Select serial console configuration */ | |
| 41 | #define CONFIG_CONS_INDEX 3 | |
| b3f4ca11 | 42 | #ifdef CONFIG_SPL_BUILD |
| c7964f86 EBS |
43 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
| 44 | #define CONFIG_SERIAL3 3 | |
| b3f4ca11 | 45 | #endif |
| c7964f86 EBS |
46 | |
| 47 | /* Physical Memory Map */ | |
| 48 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
| 49 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
| 50 | ||
| 51 | /* | |
| 52 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
| 53 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
| 54 | * This rate is divided by a local divisor. | |
| 55 | */ | |
| 56 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
| 57 | ||
| 58 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
| 59 | ||
| c7964f86 EBS |
60 | /* SPL */ |
| 61 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
| d3289aac TR |
62 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
| 63 | (64 << 20)) | |
| 64 | ||
| c7964f86 | 65 | #ifdef CONFIG_NAND |
| df4dbb5d | 66 | #define CONFIG_SYS_NAND_BASE 0x30000000 |
| c7964f86 EBS |
67 | #endif |
| 68 | ||
| 69 | /* Now bring in the rest of the common code. */ | |
| 9a0f4004 | 70 | #include <configs/ti_armv7_omap.h> |
| c7964f86 EBS |
71 | |
| 72 | #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ |