[people/ms/u-boot.git] / include / configs / trats.h

/*
 * Copyright (C) 2011 Samsung Electronics
 * Heungjun Kim <riverful.kim@samsung.com>
 *
 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
#define CONFIG_S5P		/* which is in a S5P Family */
#define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
#define CONFIG_TRATS		/* working with TRATS */
#define CONFIG_TIZEN		/* TIZEN lib */

#include <asm/arch/cpu.h>	/* get chip and board defs */

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE	0x10502000
#endif

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_TEXT_BASE		0x63300000

/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210	24000000
#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F

/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS			3928
#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (16 << 20))

/* select serial console configuration */
#define CONFIG_SERIAL2			/* use SERIAL 2 */
#define CONFIG_BAUDRATE			115200

/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI
#define CONFIG_MMC_SDMA

/* PWM */
#define CONFIG_PWM

/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH

/* Command definition */
#include <config_cmd_default.h>

#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_CACHE
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC
#define CONFIG_CMD_DFU
#define CONFIG_CMD_GPT
#define CONFIG_CMD_SETEXPR

/* FAT */
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE

/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC

/* USB Samsung's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
#define CONFIG_G_DNL_MANUFACTURER "Samsung"

#define CONFIG_BOOTDELAY		1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTARGS			"Please use defined boot"
#define CONFIG_BOOTCOMMAND		"run mmcboot"

#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
#define CONFIG_BOOTBLOCK		"10"
#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"

/* Tizen - partitions definitions */
#define PARTS_CSA		"csa-mmc"
#define PARTS_BOOTLOADER	"u-boot"
#define PARTS_BOOT		"boot"
#define PARTS_ROOT		"platform"
#define PARTS_DATA		"data"
#define PARTS_CSC		"csc"
#define PARTS_UMS		"ums"

#define PARTS_DEFAULT \
	"uuid_disk=${uuid_gpt_disk};" \
	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	"name="PARTS_BOOTLOADER",size=60MiB," \
		"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \

#define CONFIG_DFU_ALT \
	"u-boot mmc 80 400;" \
	"uImage ext4 0 2;" \
	"exynos4210-trats.dtb ext4 0 2\0"

#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootk=" \
		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
	"updatemmc=" \
		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
		"mmc boot 0 1 1 0\0" \
	"updatebackup=" \
		"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
		"mmc boot 0 1 1 0\0" \
	"updatebootb=" \
		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	"lpj=lpj=3981312\0" \
	"nfsboot=" \
		"setenv bootargs root=/dev/nfs rw " \
		"nfsroot=${nfsroot},nolock,tcp " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
		"; run bootk\0" \
	"ramfsboot=" \
		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
		"${console} ${meminfo} " \
		"initrd=0x43000000,8M ramdisk=8192\0" \
	"mmcboot=" \
		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	"verify=n\0" \
	"rootfstype=ext4\0" \
	"console=" CONFIG_DEFAULT_CONSOLE \
	"meminfo=crashkernel=32M@0x50000000\0" \
	"nfsroot=/nfsroot/arm\0" \
	"bootblock=" CONFIG_BOOTBLOCK "\0" \
	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
		"${fdtfile}\0" \
	"mmcdev=0\0" \
	"mmcbootpart=2\0" \
	"mmcrootpart=5\0" \
	"opts=always_resume=1\0" \
	"partitions=" PARTS_DEFAULT \
	"dfu_alt_info=" CONFIG_DFU_ALT \
	"spladdr=0x40000100\0" \
	"splsize=0x200\0" \
	"splfile=falcon.bin\0" \
	"spl_export=" \
		   "setexpr spl_imgsize ${splsize} + 8 ;" \
		   "setenv spl_imgsize 0x${spl_imgsize};" \
		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
		   "spl export atags 0x40007FC0;" \
		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
		   "mw.l ${spl_addr_tmp} ${splsize};" \
		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
		   "setenv spl_imgsize;" \
		   "setenv spl_imgaddr;" \
		   "setenv spl_addr_tmp;\0" \
	"fdtaddr=40800000\0" \
	"fdtfile=exynos4210-trats.dtb\0"


/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"TRATS # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)

#define CONFIG_SYS_HZ			1000

/* TRATS has 4 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS	4
#define SDRAM_BANK_SIZE		(256UL << 20UL)	/* 256 MB */
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_1_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_2		(CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
#define PHYS_SDRAM_2_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_3		(CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_3_SIZE	SDRAM_BANK_SIZE
#define PHYS_SDRAM_4		(CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
#define PHYS_SDRAM_4_SIZE	SDRAM_BANK_SIZE

#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			4096
#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */

#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION

/* EXT4 */
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
/* Falcon mode definitions */
#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR        PHYS_SDRAM_1 + 0x100

/* GPT */
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE       32

#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED	50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SOFT_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS	15

#include <asm/arch/gpio.h>

/* I2C PMIC */
#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)

/* I2C FG */
#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)

#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
#define I2C_INIT multi_i2c_init()

#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8997

#define CONFIG_POWER_FG
#define CONFIG_POWER_FG_MAX17042
#define CONFIG_POWER_MUIC
#define CONFIG_POWER_MUIC_MAX8997
#define CONFIG_POWER_BATTERY
#define CONFIG_POWER_BATTERY_TRATS
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW	2

/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_32BPP
#define CONFIG_FB_ADDR		0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))

#define CONFIG_CMD_USB_MASS_STORAGE
#if defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_USB_GADGET_MASS_STORAGE
#endif

/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT    1

#endif	/* __CONFIG_H */
Commit	Line	Data
89f95492 HK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	* Heungjun Kim <riverful.kim@samsung.com>
	4	*
	5	* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
89f95492 HK	8	*/
	9
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	/*
	14	* High Level Configuration Options
	15	* (easy to change)
	16	*/
	17	#define CONFIG_SAMSUNG /* in a SAMSUNG core */
	18	#define CONFIG_S5P /* which is in a S5P Family */
	19	#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
	20	#define CONFIG_TRATS /* working with TRATS */
90464971	21	#define CONFIG_TIZEN /* TIZEN lib */
89f95492 HK	22
	23	#include <asm/arch/cpu.h> /* get chip and board defs */
	24
	25	#define CONFIG_ARCH_CPU_INIT
	26	#define CONFIG_DISPLAY_CPUINFO
	27	#define CONFIG_DISPLAY_BOARDINFO
	28
d0460b01 ŁM	29	#ifndef CONFIG_SYS_L2CACHE_OFF
	30	#define CONFIG_SYS_L2_PL310
	31	#define CONFIG_SYS_PL310_BASE 0x10502000
	32	#endif
89f95492 HK	33
	34	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	35	#define CONFIG_SYS_TEXT_BASE 0x63300000
	36
	37	/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
	38	#define CONFIG_SYS_CLK_FREQ_C210 24000000
5e46f83c	39	#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
89f95492 HK	40
	41	#define CONFIG_SETUP_MEMORY_TAGS
	42	#define CONFIG_CMDLINE_TAG
89f95492 HK	43	#define CONFIG_REVISION_TAG
	44	#define CONFIG_CMDLINE_EDITING
	45	#define CONFIG_SKIP_LOWLEVEL_INIT
	46	#define CONFIG_BOARD_EARLY_INIT_F
	47
	48	/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
	49	#define MACH_TYPE_TRATS 3928
	50	#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
	51
	52	/* Size of malloc() pool */
9199fce2	53	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (16 << 20))
89f95492 HK	54
89f95492 HK	55	/* select serial console configuration */
89f95492 HK	56	#define CONFIG_SERIAL2 /* use SERIAL 2 */
	57	#define CONFIG_BAUDRATE 115200
	58
	59	/* MMC */
	60	#define CONFIG_GENERIC_MMC
	61	#define CONFIG_MMC
7d2d58b4 JC	62	#define CONFIG_S5P_SDHCI
7d2d58b4 JC	63	#define CONFIG_SDHCI
b09ed6e4	64	#define CONFIG_MMC_SDMA
89f95492 HK	65
	66	/* PWM */
	67	#define CONFIG_PWM
	68
	69	/* It should define before config_cmd_default.h */
	70	#define CONFIG_SYS_NO_FLASH
	71
	72	/* Command definition */
	73	#include <config_cmd_default.h>
	74
	75	#undef CONFIG_CMD_FPGA
	76	#undef CONFIG_CMD_MISC
	77	#undef CONFIG_CMD_NET
	78	#undef CONFIG_CMD_NFS
	79	#undef CONFIG_CMD_XIMG
	80	#undef CONFIG_CMD_CACHE
	81	#undef CONFIG_CMD_ONENAND
	82	#undef CONFIG_CMD_MTDPARTS
	83	#define CONFIG_CMD_MMC
93a1ab57	84	#define CONFIG_CMD_DFU
9960d9a8	85	#define CONFIG_CMD_GPT
35777e22	86	#define CONFIG_CMD_SETEXPR
93a1ab57 ŁM	87
	88	/* FAT */
	89	#define CONFIG_CMD_FAT
	90	#define CONFIG_FAT_WRITE
	91
	92	/* USB Composite download gadget - g_dnl */
	93	#define CONFIG_USBDOWNLOAD_GADGET
	94	#define CONFIG_DFU_FUNCTION
	95	#define CONFIG_DFU_MMC
	96
	97	/* USB Samsung's IDs */
	98	#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
	99	#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
	100	#define CONFIG_G_DNL_MANUFACTURER "Samsung"
89f95492 HK	101
	102	#define CONFIG_BOOTDELAY 1
	103	#define CONFIG_ZERO_BOOTDELAY_CHECK
	104	#define CONFIG_BOOTARGS "Please use defined boot"
	105	#define CONFIG_BOOTCOMMAND "run mmcboot"
	106
	107	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
	108	#define CONFIG_BOOTBLOCK "10"
	109	#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
	110
9960d9a8 ŁM	111	/* Tizen - partitions definitions */
	112	#define PARTS_CSA "csa-mmc"
	113	#define PARTS_BOOTLOADER "u-boot"
	114	#define PARTS_BOOT "boot"
	115	#define PARTS_ROOT "platform"
	116	#define PARTS_DATA "data"
	117	#define PARTS_CSC "csc"
	118	#define PARTS_UMS "ums"
	119
	120	#define PARTS_DEFAULT \
	121	"uuid_disk=${uuid_gpt_disk};" \
	122	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	123	"name="PARTS_BOOTLOADER",size=60MiB," \
	124	"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
	125	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	126	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
	127	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
	128	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
	129	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
	130
93a1ab57	131	#define CONFIG_DFU_ALT \
93a1ab57	132	"u-boot mmc 80 400;" \
ba223bb2 AW	133	"uImage ext4 0 2;" \
ba223bb2 AW	134	"exynos4210-trats.dtb ext4 0 2\0"
93a1ab57	135
89f95492 HK	136	#define CONFIG_ENV_OVERWRITE
	137	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	138	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	139
	140	#define CONFIG_EXTRA_ENV_SETTINGS \
	141	"bootk=" \
ba223bb2	142	"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
89f95492 HK	143	"updatemmc=" \
	144	"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
	145	"mmc boot 0 1 1 0\0" \
	146	"updatebackup=" \
	147	"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
	148	"mmc boot 0 1 1 0\0" \
	149	"updatebootb=" \
	150	"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	151	"lpj=lpj=3981312\0" \
	152	"nfsboot=" \
35777e22	153	"setenv bootargs root=/dev/nfs rw " \
89f95492 HK	154	"nfsroot=${nfsroot},nolock,tcp " \
	155	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	156	"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
	157	"; run bootk\0" \
	158	"ramfsboot=" \
35777e22	159	"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
89f95492 HK	160	"${console} ${meminfo} " \
	161	"initrd=0x43000000,8M ramdisk=8192\0" \
	162	"mmcboot=" \
35777e22	163	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
89f95492	164	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
ba223bb2	165	"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
35777e22	166	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
89f95492 HK	167	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	168	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	169	"verify=n\0" \
	170	"rootfstype=ext4\0" \
	171	"console=" CONFIG_DEFAULT_CONSOLE \
	172	"meminfo=crashkernel=32M@0x50000000\0" \
	173	"nfsroot=/nfsroot/arm\0" \
	174	"bootblock=" CONFIG_BOOTBLOCK "\0" \
35777e22	175	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
4ef400b9	176	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
ba223bb2	177	"${fdtfile}\0" \
89f95492 HK	178	"mmcdev=0\0" \
89f95492 HK	179	"mmcbootpart=2\0" \
35777e22	180	"mmcrootpart=5\0" \
93a1ab57	181	"opts=always_resume=1\0" \
9960d9a8	182	"partitions=" PARTS_DEFAULT \
35777e22 ŁM	183	"dfu_alt_info=" CONFIG_DFU_ALT \
	184	"spladdr=0x40000100\0" \
	185	"splsize=0x200\0" \
	186	"splfile=falcon.bin\0" \
	187	"spl_export=" \
	188	"setexpr spl_imgsize ${splsize} + 8 ;" \
dc993a65	189	"setenv spl_imgsize 0x${spl_imgsize};" \
35777e22 ŁM	190	"setexpr spl_imgaddr ${spladdr} - 8 ;" \
	191	"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
	192	"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
	193	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	194	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
	195	"spl export atags 0x40007FC0;" \
	196	"crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
	197	"mw.l ${spl_addr_tmp} ${splsize};" \
	198	"ext4write mmc ${mmcdev}:${mmcbootpart}" \
	199	" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
	200	"setenv spl_imgsize;" \
	201	"setenv spl_imgaddr;" \
ba223bb2 AW	202	"setenv spl_addr_tmp;\0" \
	203	"fdtaddr=40800000\0" \
	204	"fdtfile=exynos4210-trats.dtb\0"
	205
89f95492 HK	206
	207	/* Miscellaneous configurable options */
	208	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	209	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
89f95492 HK	210	#define CONFIG_SYS_PROMPT "TRATS # "
	211	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	212	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	213	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	214	/* Boot Argument Buffer Size */
	215	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	216	/* memtest works on */
	217	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	218	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
	219	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
	220
	221	#define CONFIG_SYS_HZ 1000
	222
b5598578 PW	223	/* TRATS has 4 banks of DRAM */
	224	#define CONFIG_NR_DRAM_BANKS 4
	225	#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
	226	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
	227	#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
	228	#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
	229	#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
	230	#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
	231	#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
	232	#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
	233	#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
89f95492 HK	234
	235	#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
	236
	237	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	238	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	239
	240	#define CONFIG_ENV_IS_IN_MMC
	241	#define CONFIG_SYS_MMC_ENV_DEV 0
	242	#define CONFIG_ENV_SIZE 4096
	243	#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
	244
	245	#define CONFIG_DOS_PARTITION
35777e22 ŁM	246	#define CONFIG_EFI_PARTITION
	247
	248	/* EXT4 */
	249	#define CONFIG_CMD_EXT4
	250	#define CONFIG_CMD_EXT4_WRITE
	251	/* Falcon mode definitions */
	252	#define CONFIG_CMD_SPL
	253	#define CONFIG_SYS_SPL_ARGS_ADDR PHYS_SDRAM_1 + 0x100
89f95492	254
9960d9a8 ŁM	255	/* GPT */
	256	#define CONFIG_EFI_PARTITION
	257	#define CONFIG_PARTITION_UUIDS
	258
89f95492 HK	259	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
	260	#define CONFIG_SYS_CACHELINE_SIZE 32
	261
89f95492 HK	262	#define CONFIG_SOFT_I2C
89f95492 HK	263	#define CONFIG_SOFT_I2C_READ_REPEATED_START
fd8dca83	264	#define CONFIG_SYS_I2C_INIT_BOARD
89f95492 HK	265	#define CONFIG_SYS_I2C_SPEED 50000
89f95492 HK	266	#define CONFIG_I2C_MULTI_BUS
fd8dca83 ŁM	267	#define CONFIG_SOFT_I2C_MULTI_BUS
	268	#define CONFIG_SYS_MAX_I2C_BUS 15
	269
	270	#include <asm/arch/gpio.h>
	271
	272	/* I2C PMIC */
	273	#define CONFIG_SOFT_I2C_I2C5_SCL exynos4_gpio_part1_get_nr(b, 7)
	274	#define CONFIG_SOFT_I2C_I2C5_SDA exynos4_gpio_part1_get_nr(b, 6)
	275
	276	/* I2C FG */
	277	#define CONFIG_SOFT_I2C_I2C9_SCL exynos4_gpio_part2_get_nr(y4, 1)
	278	#define CONFIG_SOFT_I2C_I2C9_SDA exynos4_gpio_part2_get_nr(y4, 0)
	279
	280	#define CONFIG_SOFT_I2C_GPIO_SCL get_multi_scl_pin()
	281	#define CONFIG_SOFT_I2C_GPIO_SDA get_multi_sda_pin()
	282	#define I2C_INIT multi_i2c_init()
89f95492	283
be3b51aa ŁM	284	#define CONFIG_POWER
	285	#define CONFIG_POWER_I2C
	286	#define CONFIG_POWER_MAX8997
89f95492	287
5a77358c ŁM	288	#define CONFIG_POWER_FG
5a77358c ŁM	289	#define CONFIG_POWER_FG_MAX17042
7dcda99d ŁM	290	#define CONFIG_POWER_MUIC
7dcda99d ŁM	291	#define CONFIG_POWER_MUIC_MAX8997
61365ffc ŁM	292	#define CONFIG_POWER_BATTERY
61365ffc ŁM	293	#define CONFIG_POWER_BATTERY_TRATS
89f95492 HK	294	#define CONFIG_USB_GADGET
	295	#define CONFIG_USB_GADGET_S3C_UDC_OTG
	296	#define CONFIG_USB_GADGET_DUALSPEED
93a1ab57	297	#define CONFIG_USB_GADGET_VBUS_DRAW 2
89f95492	298
51b1cd6d DL	299	/* LCD */
	300	#define CONFIG_EXYNOS_FB
	301	#define CONFIG_LCD
90464971 DL	302	#define CONFIG_CMD_BMP
90464971 DL	303	#define CONFIG_BMP_32BPP
51b1cd6d DL	304	#define CONFIG_FB_ADDR 0x52504000
	305	#define CONFIG_S6E8AX0
	306	#define CONFIG_EXYNOS_MIPI_DSIM
90464971 DL	307	#define CONFIG_VIDEO_BMP_GZIP
90464971 DL	308	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
51b1cd6d	309
83301b4f ŁM	310	#define CONFIG_CMD_USB_MASS_STORAGE
	311	#if defined(CONFIG_CMD_USB_MASS_STORAGE)
	312	#define CONFIG_USB_GADGET_MASS_STORAGE
	313	#endif
	314
ba223bb2 AW	315	/* Pass open firmware flat tree */
	316	#define CONFIG_OF_LIBFDT 1
	317
89f95492	318	#endif /* __CONFIG_H */